Merge branch 'master' into internal

stv090x: removed duplicate function
Version 0.9.25
2025-03-01 10:35:23 +00:00 · 2016-08-31 22:25:54 +02:00 · 2016-08-31 22:24:37 +02:00 · 2016-08-31 19:10:39 +02:00 · 2016-08-31 19:10:23 +02:00 · 2016-08-31 18:46:07 +02:00
9 changed files with 546 additions and 316 deletions
--- a/apps/flashprog.c
+++ b/apps/flashprog.c
@@ -569,6 +569,10 @@ int main(int argc, char **argv)
 		type = 6;
 	if (ddbid.device == 0x12)
 		type = 7;
+	if (ddbid.device == 0x08)
+		type = 8;
+	if (ddbid.device == 0x210)
+		type = 9;
 	
 	if (!SectorSize)
 		return 0;
@@ -632,7 +636,11 @@ int main(int argc, char **argv)
 			printf("Octopus 35\n");
 			break;
 		case 4:
-			fname="DVBBridgeV2A_DD01_0007_MXL.bit";
+			fname="DVBBridgeV2A_DD01_0007_MXL.fpga";
+			printf("Octopus 4/8\n");
+			break;
+		case 8:
+			fname="DVBBridgeV2A_DD01_0008_CXD.fpga";
 			printf("Octopus 4/8\n");
 			break;
 		case 6:
@@ -643,6 +651,10 @@ int main(int argc, char **argv)
 			fname="DVBBridgeV2B_DD01_0012_STD.fpga";
 			printf("Octopus CI\n");
 			break;
+		case 9:
+			fname="DVBModulatorV2A_DD01_0210.fpga";
+			printf("Modulator V2\n");
+			break;
 		default:
 			printf("UNKNOWN\n");
 			break;
--- a/ddbridge/ddbridge-core.c
+++ b/ddbridge/ddbridge-core.c
@@ -285,7 +285,6 @@ static struct ddb_regmap octopus_mod_map = {
 	.channel = &octopus_mod_channel,
 };

-
 static struct ddb_regmap octopus_mod_2_map = {
 	.irq_version = 2,
 	.irq_base_odma = 64,
@@ -306,17 +305,67 @@ static struct ddb_info ddb_s2_48 = {
 	.port_num = 4,
 	.i2c_mask = 0x01,
 	.board_control = 1,
+	.tempmon_irq = 24,
 };

-static struct ddb_info ddb_ct_8 = {
+static struct ddb_info ddb_ct2_8 = {
 	.type     = DDB_OCTOPUS_MAX_CT,
-	.name     = "Digital Devices MAX CT8",
+	.name     = "Digital Devices MAX A8 CT2",
 	.regmap   = &octopus_map,
 	.port_num = 4,
 	.i2c_mask = 0x0f,
 	.board_control   = 0x0ff,
 	.board_control_2 = 0xf00,
 	.ts_quirks = TS_QUIRK_SERIAL,
+	.tempmon_irq = 24,
+};
+
+static struct ddb_info ddb_c2t2_8 = {
+	.type     = DDB_OCTOPUS_MAX_CT,
+	.name     = "Digital Devices MAX A8 C2T2",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 0x0ff,
+	.board_control_2 = 0xf00,
+	.ts_quirks = TS_QUIRK_SERIAL,
+	.tempmon_irq = 24,
+};
+
+static struct ddb_info ddb_isdbt_8 = {
+	.type     = DDB_OCTOPUS_MAX_CT,
+	.name     = "Digital Devices MAX A8 ISDBT",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 0x0ff,
+	.board_control_2 = 0xf00,
+	.ts_quirks = TS_QUIRK_SERIAL,
+	.tempmon_irq = 24,
+};
+
+static struct ddb_info ddb_c2t2i_v0_8 = {
+	.type     = DDB_OCTOPUS_MAX_CT,
+	.name     = "Digital Devices MAX A8 C2T2I V0",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 0x0ff,
+	.board_control_2 = 0xf00,
+	.ts_quirks = TS_QUIRK_SERIAL,
+	.tempmon_irq = 24,
+};
+
+static struct ddb_info ddb_c2t2i_8 = {
+	.type     = DDB_OCTOPUS_MAX_CT,
+	.name     = "Digital Devices MAX A8 C2T2I",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 0x0ff,
+	.board_control_2 = 0xf00,
+	.ts_quirks = TS_QUIRK_SERIAL,
+	.tempmon_irq = 24,
 };


@@ -2601,6 +2650,11 @@ static void ddb_port_probe(struct ddb_port *port)
 			port->type = DDB_TUNER_ISDBT_SONY_P;
 			port->type_name = "ISDBT_SONY";
 			break;
+		case 0xc1:
+			port->name = "DUAL DVB-C2T2 ISDB-T CXD2854";
+			port->type = DDB_TUNER_DVBC2T2_SONY_P;
+			port->type_name = "DVBC2T2_ISDBT_SONY";
+			break;
 		default:
 			return;
 		}
@@ -4359,15 +4413,28 @@ static ssize_t fan_store(struct device *device, struct device_attribute *d,
 	return count;
 }

+static ssize_t fanspeed_show(struct device *device,
+			 struct device_attribute *attr, char *buf)
+{
+	struct ddb *dev = dev_get_drvdata(device);
+	int num = attr->attr.name[8] - 0x30;
+	struct ddb_link *link = &dev->link[num];
+	u32 spd;
+
+	spd = ddblreadl(link, TEMPMON_FANCONTROL) & 0xff;
+	return sprintf(buf, "%u\n", spd * 100);
+}
+
 static ssize_t temp_show(struct device *device,
 			 struct device_attribute *attr, char *buf)
 {
 	struct ddb *dev = dev_get_drvdata(device);
+	struct ddb_link *link = &dev->link[0];
 	struct i2c_adapter *adap;
 	s32 temp, temp2, temp3;
 	int i;
 	u8 tmp[2];
-
+	
 	if (dev->link[0].info->type == DDB_MOD) {
 		if (dev->link[0].info->version == 2) {
 			temp = ddbreadl(dev, TEMPMON2_BOARD);
@@ -4849,6 +4916,13 @@ static struct device_attribute ddb_attrs_led[] = {
 	__ATTR(led3, 0664, led_show, led_store),
 };

+static struct device_attribute ddb_attrs_fanspeed[] = {
+	__ATTR_MRO(fanspeed0, fanspeed_show),
+	__ATTR_MRO(fanspeed1, fanspeed_show),
+	__ATTR_MRO(fanspeed2, fanspeed_show),
+	__ATTR_MRO(fanspeed3, fanspeed_show),
+};
+
 static struct class ddb_class = {
 	.name		= "ddbridge",
 	.owner          = THIS_MODULE,
@@ -4878,6 +4952,10 @@ static void ddb_device_attrs_del(struct ddb *dev)
 {
 	int i;

+	for (i = 0; i < 4; i++)
+		if (dev->link[i].info &&
+		    dev->link[i].info->tempmon_irq)
+			device_remove_file(dev->ddb_dev, &ddb_attrs_fanspeed[i]);
 	for (i = 0; i < dev->link[0].info->temp_num; i++)
 		device_remove_file(dev->ddb_dev, &ddb_attrs_temp[i]);
 	for (i = 0; i < dev->link[0].info->port_num; i++)
@@ -4920,6 +4998,12 @@ static int ddb_device_attrs_add(struct ddb *dev)
 					       &ddb_attrs_led[i]))
 				goto fail;
 	}
+	for (i = 0; i < 4; i++)
+		if (dev->link[i].info &&
+		    dev->link[i].info->tempmon_irq)
+			if (device_create_file(dev->ddb_dev,
+					       &ddb_attrs_fanspeed[i]))
+				goto fail;
 	return 0;
 fail:
 	return -1;
@@ -4994,6 +5078,7 @@ static void link_tasklet(unsigned long data)
 	LINK_IRQ_HANDLE(l, 1);
 	LINK_IRQ_HANDLE(l, 2);
 	LINK_IRQ_HANDLE(l, 3);
+	LINK_IRQ_HANDLE(l, 24);
 }

 static void gtl_irq_handler(unsigned long priv)
@@ -5010,6 +5095,7 @@ static void gtl_irq_handler(unsigned long priv)
 		LINK_IRQ_HANDLE(l, 1);
 		LINK_IRQ_HANDLE(l, 2);
 		LINK_IRQ_HANDLE(l, 3);
+		LINK_IRQ_HANDLE(l, 24);
 	}
 #else
 	tasklet_schedule(&link->tasklet);
@@ -5054,7 +5140,7 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
 		link->info = &ddb_s2_48;
 		break;
 	case 0x0008dd01:
-		link->info = &ddb_ct_8;
+		link->info = &ddb_c2t2_8;
 		break;
 	default:
 		pr_info("DDBridge: Detected GT link but found invalid ID %08x. You might have to update (flash) the add-on card first.",
@@ -5068,16 +5154,24 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
 	dev->handler_data[0][base + l] = (unsigned long) link;
 	dev->handler[0][base + l] = gtl_irq_handler;

+	dev->link[l].ids.hwid = ddbreadl(dev, DDB_LINK_TAG(l) | 0);
+	dev->link[l].ids.regmapid = ddbreadl(dev, DDB_LINK_TAG(l) | 4);
+	dev->link[l].ids.vendor = id >> 16;;
+	dev->link[l].ids.device = id & 0xffff;;
+	//dev->link[l].ids.subvendor = id->subvendor;
+	//dev->link[l].ids.subdevice = id->subdevice;
+
 	pr_info("GTL %s\n", dev->link[l].info->name);
+
 	pr_info("GTL HW %08x REGMAP %08x\n",
-		ddbreadl(dev, DDB_LINK_TAG(l) | 0),
-		ddbreadl(dev, DDB_LINK_TAG(l) | 4));
+		dev->link[l].ids.hwid,
+		dev->link[l].ids.regmapid);
 	pr_info("GTL ID %08x\n",
 		ddbreadl(dev, DDB_LINK_TAG(l) | 8));

 	tasklet_init(&link->tasklet, link_tasklet, (unsigned long) link);
 	ddbwritel(dev, 0xffffffff, DDB_LINK_TAG(l) | INTERRUPT_ACK);
-	ddbwritel(dev, 0xf, DDB_LINK_TAG(l) | INTERRUPT_ENABLE);
+	ddbwritel(dev, 0x0100000f, DDB_LINK_TAG(l) | INTERRUPT_ENABLE);

 	return 0;
 }
@@ -5093,13 +5187,110 @@ static int ddb_gtl_init(struct ddb *dev)
 	return 0;
 }

+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static void tempmon_setfan(struct ddb_link *link)
+{
+	u32 temp, temp2, pwm;
+	
+	if ((ddblreadl(link, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) {
+		pr_info("Over temperature condition\n");
+		link->OverTemperatureError = 1;
+	}
+	temp  = (ddblreadl(link, TEMPMON_SENSOR0) >> 8) & 0xFF;
+	if (temp & 0x80)
+		temp = 0;
+	temp2  = (ddblreadl(link, TEMPMON_SENSOR1) >> 8) & 0xFF;
+	if (temp2 & 0x80)
+		temp2 = 0;
+	if (temp2 > temp)
+		temp = temp2;
+	
+	pwm = (ddblreadl(link, TEMPMON_FANCONTROL) >> 8) & 0x0F;
+	if (pwm > 10)
+		pwm = 10;   
+	
+	if (temp >= link->temp_tab[pwm]) {
+		while( pwm < 10 && temp >= link->temp_tab[pwm + 1])
+			pwm += 1;
+	} else {
+		while( pwm > 1 && temp < link->temp_tab[pwm - 2])
+			pwm -= 1;
+	}
+	ddblwritel(link, (pwm << 8), TEMPMON_FANCONTROL);
+ }
+
+
+static void temp_handler(unsigned long data)
+{
+	struct ddb_link *link = (struct ddb_link *) data;
+
+	spin_lock(&link->temp_lock);
+	tempmon_setfan(link);
+	spin_unlock(&link->temp_lock);
+}
+
+static int tempmon_init(struct ddb_link *link, int FirstTime)
+{
+	struct ddb *dev = link->dev;
+	int status = 0;
+	u32 l = link->nr;
+	
+	spin_lock_irq(&link->temp_lock);
+	if (FirstTime) {
+		static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80};
+		
+		memcpy(link->temp_tab, TemperatureTable, sizeof(TemperatureTable));
+	}
+	dev->handler[l][link->info->tempmon_irq] = temp_handler;
+	dev->handler_data[l][link->info->tempmon_irq] = (unsigned long) link;
+	ddblwritel(link, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN |
+			  TEMPMON_CONTROL_INTENABLE),
+		   TEMPMON_CONTROL);
+	ddblwritel(link, (3 << 8), TEMPMON_FANCONTROL);
+	
+	link->OverTemperatureError =
+		((ddblreadl(link, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0);
+	if (link->OverTemperatureError)	{
+		pr_info("Over temperature condition\n");
+		status = -1;
+	}
+	tempmon_setfan(link);
+	spin_unlock_irq(&link->temp_lock);
+	return status;
+}
+
+static int ddb_init_tempmon(struct ddb_link *link)
+{
+	struct ddb *dev = link->dev;
+	struct ddb_info *info = link->info;
+	
+	if (!info->tempmon_irq)
+		return;
+	if (info->type == DDB_OCTOPUS_MAX ||
+	     info->type == DDB_OCTOPUS_MAX_CT)
+		if (link->ids.regmapid < 0x00010002)
+			return;
+	spin_lock_init(&link->temp_lock);
+	printk("init_tempmon\n");
+	tempmon_init(link, 1);
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
 static int ddb_init_boards(struct ddb *dev)
 {
 	struct ddb_info *info;
+	struct ddb_link *link;
 	u32 l;

 	for (l = 0; l < DDB_MAX_LINK; l++) {
-		info = dev->link[l].info;
+		link = &dev->link[l];
+		info = link->info;
 		if (!info)
 			continue;
 		if (info->board_control) {
@@ -5113,6 +5304,7 @@ static int ddb_init_boards(struct ddb *dev)
 				  DDB_LINK_TAG(l) | BOARD_CONTROL);
 			usleep_range(2000, 3000);
 		}
+		ddb_init_tempmon(link);
 	}
 	return 0;
 }
--- a/ddbridge/ddbridge-mod.c
+++ b/ddbridge/ddbridge-mod.c
@@ -215,12 +215,12 @@ static void mod_set_rateinc(struct ddb *dev, u32 chan)

 static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 };

-void ddbridge_mod_output_start(struct ddb_output *output)
+int ddbridge_mod_output_start(struct ddb_output *output)
 {
 	struct ddb *dev = output->port->dev;
 	u32 Channel = output->nr;
 	struct ddb_mod *mod = &dev->mod[output->nr];
-	u32 Symbolrate = 6900000;
+	u32 Symbolrate = mod->symbolrate;
 	
 	/*PCRIncrement = RoundPCR(PCRIncrement);*/
 	/*PCRDecrement = RoundPCR(PCRDecrement);*/
@@ -256,8 +256,7 @@ void ddbridge_mod_output_start(struct ddb_output *output)
 		u32 d = gcd(KF,LF);
 		u32 checkLF;

-		mod->modulation = QAM_256 - 1;
-		ddbwritel(dev, mod->modulation, CHANNEL_SETTINGS(Channel));
+		ddbwritel(dev, mod->modulation - 1, CHANNEL_SETTINGS(Channel));
 		ddbwritel(dev, Output, CHANNEL_SETTINGS2(Channel));
 		
 		KF = KF / d;
@@ -297,6 +296,7 @@ void ddbridge_mod_output_start(struct ddb_output *output)
 		if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_UNMUTE))
 			return -EINVAL;
 	pr_info("mod_output_start %d.%d\n", dev->nr, output->nr);
+	return 0;
 }

 /****************************************************************************/
@@ -422,14 +422,14 @@ static int mod_get_vga(struct ddb *dev, u32 *pGain)
 	*pGain = ddbreadl(dev, RF_VGA);
 	return 0;
 }
-
-static void mod_TemperatureMonitorSetFan(struct ddb *dev)
+#if 0
+static void TemperatureMonitorSetFan(struct ddb *dev)
 {
 	u32 tqam, pwm;
 	
 	if ((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) {
 		pr_info("Over temperature condition\n");
-		dev->mod_base.OverTemperatureError = 1;
+		dev->OverTemperatureError = 1;
 	}
 	tqam  = (ddbreadl(dev, TEMPMON2_QAMCORE) >> 8) & 0xFF;
 	if (tqam & 0x80)
@@ -439,55 +439,55 @@ static void mod_TemperatureMonitorSetFan(struct ddb *dev)
 	if (pwm > 10)
 		pwm = 10;   
 	
-	if (tqam >= dev->mod_base.temp_tab[pwm]) {
-		while( pwm < 10 && tqam >= dev->mod_base.temp_tab[pwm + 1])
+	if (tqam >= dev->temp_tab[pwm]) {
+		while( pwm < 10 && tqam >= dev->temp_tab[pwm + 1])
 			pwm += 1;
 	} else {
-		while( pwm > 1 && tqam < dev->mod_base.temp_tab[pwm - 2])
+		while( pwm > 1 && tqam < dev->temp_tab[pwm - 2])
 			pwm -= 1;
 	}
 	ddbwritel(dev, (pwm << 8), TEMPMON_FANCONTROL);
 }


-static void mod_temp_handler(unsigned long data)
+static void temp_handler(unsigned long data)
 {
 	struct ddb *dev = (struct ddb *) data;

-	pr_info("mod_temp_handler\n");
+	pr_info("temp_handler\n");

-	spin_lock(&dev->mod_base.temp_lock);
-	mod_TemperatureMonitorSetFan(dev);
-	spin_unlock(&dev->mod_base.temp_lock);
+	spin_lock(&dev->temp_lock);
+	TemperatureMonitorSetFan(dev);
+	spin_unlock(&dev->temp_lock);
 }

-static int mod_TemperatureMonitorInit(struct ddb *dev, int FirstTime) {
+static int TemperatureMonitorInit(struct ddb *dev, int FirstTime) {
 	int status = 0;
 	
-	spin_lock_irq(&dev->mod_base.temp_lock);
+	spin_lock_irq(&dev->temp_lock);
 	if (FirstTime) {
 		static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80};
 		
-		memcpy(dev->mod_base.temp_tab, TemperatureTable, sizeof(TemperatureTable));
+		memcpy(dev->temp_tab, TemperatureTable, sizeof(TemperatureTable));
 	}
-	dev->handler[0][8] = mod_temp_handler;
+	dev->handler[0][8] = temp_handler;
 	dev->handler_data[0][8] = (unsigned long) dev;
 	ddbwritel(dev, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN |
 			TEMPMON_CONTROL_INTENABLE),
 		  TEMPMON_CONTROL);
 	ddbwritel(dev, (3 << 8), TEMPMON_FANCONTROL);
 	
-	dev->mod_base.OverTemperatureError =
+	dev->OverTemperatureError =
 		((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0);
-	if (dev->mod_base.OverTemperatureError)	{
+	if (dev->OverTemperatureError)	{
 		pr_info("Over temperature condition\n");
 		status = -1;
 	}
-	mod_TemperatureMonitorSetFan(dev);
-	spin_unlock_irq(&dev->mod_base.temp_lock);
+	TemperatureMonitorSetFan(dev);
+	spin_unlock_irq(&dev->temp_lock);
 	return status;
 }
-
+#endif
 /****************************************************************************/
 /****************************************************************************/
 /****************************************************************************/
@@ -1063,14 +1063,27 @@ u32 eqtab[] = {
 	0x00001B23, 0x0000EEB7, 0x00006A28
 };

-static int mod_set_modulation(struct ddb *dev, int chan, enum fe_modulation mod)
+static int mod_set_modrate(struct ddb *dev, int chan,
+			   enum fe_modulation mod, u32 srate)
 {
+	u64 ofac; 
+
 	if (mod > QAM_256 || mod < QAM_16)
 		return -EINVAL;
+	if (dev->link[0].info->version < 2) {
+		if (srate != 6900000)
+			return -EINVAL;
+	} else {
+		if (srate > 7100000)
+			return -EINVAL;
+	}
+	dev->mod[chan].symbolrate = srate;
 	dev->mod[chan].modulation = mod;
-	dev->mod[chan].obitrate = 0x0061072787900000ULL * (mod + 3);
+	ofac = ((((u64) srate) << 32) * 188 ) / 204;
+	dev->mod[chan].obitrate = ofac * (mod + 3);
 	dev->mod[chan].ibitrate = dev->mod[chan].obitrate;
-	ddbwritel(dev, qamtab[mod], CHANNEL_SETTINGS(chan));
+	if (dev->link[0].info->version < 2) 
+		ddbwritel(dev, qamtab[mod], CHANNEL_SETTINGS(chan));
 	return 0;
 }

@@ -1179,9 +1192,10 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)

 		iqfreq = flash->DataSet[0].FrequencyFactor *
 			(FrequencyCH10 + (9 - i) * 8);
+		iqfreq += (dev->link[0].ids.hwid == 0x0203dd01) ? 22 : 0 ;
 		iqsteps = flash->DataSet[0].IQTableLength;
 		mod_set_iq(dev, iqsteps, i, iqfreq);
-		mod_set_modulation(dev, i, QAM_256);
+		mod_set_modrate(dev, i, QAM_256, 6900000);
 	}

 	mod_bypass_equalizer(dev, 1);
@@ -1390,158 +1404,26 @@ void ddbridge_mod_rate_handler(unsigned long data)
 		PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement);
 }

-static int mod_ioctl_1(struct file *file, unsigned int cmd, void *parg)
+static void mod_calc_rateinc(struct ddb_mod *mod)
 {
-	struct dvb_device *dvbdev = file->private_data;
-	struct ddb_output *output = dvbdev->priv;
-	struct ddb *dev = output->port->dev;
-
-	/* unsigned long arg = (unsigned long) parg; */
-	int ret = 0;
-
-	switch (cmd) {
-	case DVB_MOD_SET:
-	{
-		struct dvb_mod_params *mp = parg;
-
-		pr_info("set base freq\n");
-		if (mp->base_frequency != dev->mod_base.frequency)
-			if (set_base_frequency(dev, mp->base_frequency))
-				return -EINVAL;
-		pr_info("set attenuator\n");
-		mod_set_attenuator(dev, mp->attenuator);
-		break;
-	}
-	case DVB_MOD_CHANNEL_SET:
-	{
-		struct dvb_mod_channel_params *cp = parg;
-		int res;
-		u32 ri;
-
-		pr_info("set modulation\n");
-		res = mod_set_modulation(dev, output->nr, cp->modulation);
-		if (res)
-			return res;
-
-		if (cp->input_bitrate > dev->mod[output->nr].obitrate)
-			return -EINVAL;
-		dev->mod[output->nr].ibitrate = cp->input_bitrate;
-		dev->mod[output->nr].pcr_correction = cp->pcr_correction;
-
-		pr_info("ibitrate %llu\n", dev->mod[output->nr].ibitrate);
-		pr_info("obitrate %llu\n", dev->mod[output->nr].obitrate);
-		if (cp->input_bitrate != 0) {
-			u64 d = dev->mod[output->nr].obitrate -
-				dev->mod[output->nr].ibitrate;
-
-			d = div64_u64(d, dev->mod[output->nr].obitrate >> 24);
-			if (d > 0xfffffe)
-				ri = 0xfffffe;
-			else
-				ri = d;
-		} else
-			ri = 0;
-		dev->mod[output->nr].rate_inc = ri;
-		pr_info("ibr=%llu, obr=%llu, ri=0x%06x\n",
-			dev->mod[output->nr].ibitrate >> 32,
-			dev->mod[output->nr].obitrate >> 32,
-			ri);
-		break;
-	}
-	default:
-		ret = -EINVAL;
-		break;
-	}
-	return ret;
-}
-
-
-/****************************************************************************/
-/****************************************************************************/
-/****************************************************************************/
-
-static int mod_ioctl_2(struct file *file, unsigned int cmd, void *parg)
-{
-	struct dvb_device *dvbdev = file->private_data;
-	struct ddb_output *output = dvbdev->priv;
-	struct ddb *dev = output->port->dev;
-
-	/* unsigned long arg = (unsigned long) parg; */
-	int ret = 0;
-
-	switch (cmd) {
-	case DVB_MOD_SET:
-	{
-		struct dvb_mod_params *mp = parg;
-
-		pr_info("set base freq\n");
-		dev->mod_base.frequency = mp->base_frequency;
-		pr_info("set attenuator\n");
-		mod_set_attenuator(dev, mp->attenuator);
-		break;
-	}
-	case DVB_MOD_CHANNEL_SET:
-	{
-		struct dvb_mod_channel_params *cp = parg;
-		int res;
-		u32 ri;
-
-		pr_info("set modulation\n");
-		res = mod_set_modulation(dev, output->nr, cp->modulation);
-		if (res)
-			return res;
-
-		if (cp->input_bitrate > dev->mod[output->nr].obitrate)
-			return -EINVAL;
-		dev->mod[output->nr].ibitrate = cp->input_bitrate;
-		dev->mod[output->nr].pcr_correction = cp->pcr_correction;
-
-		pr_info("ibitrate %llu\n", dev->mod[output->nr].ibitrate);
-		pr_info("obitrate %llu\n", dev->mod[output->nr].obitrate);
-		if (cp->input_bitrate != 0) {
-			u64 d = dev->mod[output->nr].obitrate -
-				dev->mod[output->nr].ibitrate;
-
-			d = div64_u64(d, dev->mod[output->nr].obitrate >> 24);
-			if (d > 0xfffffe)
-				ri = 0xfffffe;
-			else
-				ri = d;
-		} else
-			ri = 0;
-		dev->mod[output->nr].rate_inc = ri;
-		pr_info("ibr=%llu, obr=%llu, ri=0x%06x\n",
-			dev->mod[output->nr].ibitrate >> 32,
-			dev->mod[output->nr].obitrate >> 32,
-			ri);
-		break;
-	}
-	default:
-		ret = -EINVAL;
-		break;
-	}
-	return ret;
-}
-
-
-static int mod_init_2(struct ddb *dev, u32 Frequency)
-{
-	int status;
-	int streams = dev->link[0].info->port_num;
-
-	dev->mod_base.frequency = Frequency;
-	mod_TemperatureMonitorInit(dev, 1);
-	status = mod_fsm_setup(dev, 0, 0);
-
-	if (streams <= 8)
-		mod_set_vga(dev, RF_VGA_GAIN_N8);
-	else if (streams <= 16)
-		mod_set_vga(dev, RF_VGA_GAIN_N16);
-	else
-		mod_set_vga(dev, RF_VGA_GAIN_N24);
-
-	mod_set_attenuator(dev, 0);
-	return 0;
+	u32 ri;
+	
+	pr_info("ibitrate %llu\n", mod->ibitrate);
+	pr_info("obitrate %llu\n", mod->obitrate);
+	
+	if (mod->ibitrate != 0) {
+		u64 d = mod->obitrate - mod->ibitrate;
+		
+		d = div64_u64(d, mod->obitrate >> 24);
+		if (d > 0xfffffe)
+			ri = 0xfffffe;
+		else
+			ri = d;
+	} else
+		ri = 0;
+	mod->rate_inc = ri;
+	pr_info("ibr=%llu, obr=%llu, ri=0x%06x\n",
+		mod->ibitrate >> 32, mod->obitrate >> 32, ri);
 }

 int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
@@ -1549,17 +1431,73 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
 	struct dvb_device *dvbdev = file->private_data;
 	struct ddb_output *output = dvbdev->priv;
 	struct ddb *dev = output->port->dev;
+
+	/* unsigned long arg = (unsigned long) parg; */
+	int ret = 0;
+
+	switch (cmd) {
+	case DVB_MOD_SET:
+	{
+		struct dvb_mod_params *mp = parg;
+
+		if (dev->link[0].info->version < 2) {
+			if (mp->base_frequency != dev->mod_base.frequency)
+				if (set_base_frequency(dev, mp->base_frequency))
+					return -EINVAL;
+		} else {
+			dev->mod_base.frequency = mp->base_frequency;
+		}
+		mod_set_attenuator(dev, mp->attenuator);
+		break;
+	}
+	case DVB_MOD_CHANNEL_SET:
+	{
+		struct dvb_mod_channel_params *cp = parg;
+		int res;
+
+		res = mod_set_modrate(dev, output->nr, cp->modulation, 6900000);
+		if (res)
+			return res;
+
+		if (cp->input_bitrate > dev->mod[output->nr].obitrate)
+			return -EINVAL;
+		dev->mod[output->nr].ibitrate = cp->input_bitrate;
+		dev->mod[output->nr].pcr_correction = cp->pcr_correction;
+
+		mod_calc_rateinc(&dev->mod[output->nr]);
+		break;
+	}
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static int mod_init_2(struct ddb *dev, u32 Frequency)
+{
+	int status, i;
+	int streams = dev->link[0].info->port_num;
+
+	dev->mod_base.frequency = Frequency;
+	status = mod_fsm_setup(dev, 0, 0);
+
+	for (i = 0; i < streams; i++)
+		mod_set_modrate(dev, i, QAM_256, 6900000);
 	
-	if (dev->link[0].info->version <= 0)
-		return mod_ioctl_1(file, cmd, parg);
-	if (dev->link[0].info->version == 2)
-		return mod_ioctl_2(file, cmd, parg);
-	return -1;
+	if (streams <= 8)
+		mod_set_vga(dev, RF_VGA_GAIN_N8);
+	else if (streams <= 16)
+		mod_set_vga(dev, RF_VGA_GAIN_N16);
+	else
+		mod_set_vga(dev, RF_VGA_GAIN_N24);
+	
+	mod_set_attenuator(dev, 0);
+	return 0;
 }

 int ddbridge_mod_init(struct ddb *dev)
 {
-	spin_lock_init(&dev->mod_base.temp_lock);
 	if (dev->link[0].info->version <= 1)
 		return mod_init_1(dev, 722000000);
 	if (dev->link[0].info->version == 2)
--- a/ddbridge/ddbridge-regs.h
+++ b/ddbridge/ddbridge-regs.h
@@ -147,7 +147,7 @@
 #define DAC_CONTROL_RESET           (0x200)

 /* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */
-#define TEMPMON_BASE        (0xA0)
+#define TEMPMON_BASE        (0x1c0)
 #define TEMPMON_CONTROL    (TEMPMON_BASE + 0x00)

 #define TEMPMON_CONTROL_SCAN        (0x00000001)
--- a/ddbridge/ddbridge.c
+++ b/ddbridge/ddbridge.c
@@ -475,6 +475,7 @@ static struct ddb_info ddb_mod_fsm_24 = {
 	.regmap   = &octopus_mod_2_map,
 	.port_num = 24,
 	.temp_num = 1,
+	.tempmon_irq = 8,
 };

 static struct ddb_info ddb_mod_fsm_16 = {
@@ -484,6 +485,7 @@ static struct ddb_info ddb_mod_fsm_16 = {
 	.regmap   = &octopus_mod_2_map,
 	.port_num = 16,
 	.temp_num = 1,
+	.tempmon_irq = 8,
 };

 static struct ddb_info ddb_mod_fsm_8 = {
@@ -493,6 +495,7 @@ static struct ddb_info ddb_mod_fsm_8 = {
 	.regmap   = &octopus_mod_2_map,
 	.port_num = 8,
 	.temp_num = 1,
+	.tempmon_irq = 8,
 };

 static struct ddb_info ddb_octopro_hdin = {
@@ -541,15 +544,18 @@ static const struct pci_device_id ddb_id_tbl[] __devinitconst = {
 	DDB_ID(DDVID, 0x0006, DDVID, 0x0032, ddb_ctv7),
 	DDB_ID(DDVID, 0x0006, DDVID, 0x0033, ddb_ctv7),
 	DDB_ID(DDVID, 0x0007, DDVID, 0x0023, ddb_s2_48),
-	DDB_ID(DDVID, 0x0008, DDVID, 0x0034, ddb_ct_8),
-	DDB_ID(DDVID, 0x0008, DDVID, 0x0035, ddb_ct_8),
-	DDB_ID(DDVID, 0x0008, DDVID, 0x0036, ddb_ct_8),
+	DDB_ID(DDVID, 0x0008, DDVID, 0x0034, ddb_ct2_8),
+	DDB_ID(DDVID, 0x0008, DDVID, 0x0035, ddb_c2t2_8),
+	DDB_ID(DDVID, 0x0008, DDVID, 0x0036, ddb_isdbt_8),
+	DDB_ID(DDVID, 0x0008, DDVID, 0x0037, ddb_c2t2i_v0_8),
+	DDB_ID(DDVID, 0x0008, DDVID, 0x0038, ddb_c2t2i_8),
 	DDB_ID(DDVID, 0x0011, DDVID, 0x0040, ddb_ci),
 	DDB_ID(DDVID, 0x0011, DDVID, 0x0041, ddb_cis),
 	DDB_ID(DDVID, 0x0012, DDVID, 0x0042, ddb_ci),
 	DDB_ID(DDVID, 0x0013, DDVID, 0x0043, ddb_ci_s2_pro),
 	DDB_ID(DDVID, 0x0201, DDVID, 0x0001, ddb_mod),
 	DDB_ID(DDVID, 0x0201, DDVID, 0x0002, ddb_mod),
+	DDB_ID(DDVID, 0x0203, DDVID, 0x0001, ddb_mod),
 	DDB_ID(DDVID, 0x0210, DDVID, 0x0001, ddb_mod_fsm_24),
 	DDB_ID(DDVID, 0x0210, DDVID, 0x0002, ddb_mod_fsm_16),
 	DDB_ID(DDVID, 0x0210, DDVID, 0x0003, ddb_mod_fsm_8),
--- a/ddbridge/ddbridge.h
+++ b/ddbridge/ddbridge.h
@@ -113,7 +113,7 @@ struct ddb_regmap {
 	u32 irq_base_odma;
 	u32 irq_base_gtl;
 	u32 irq_base_rate;
-	
+
 	struct ddb_regset *i2c;
 	struct ddb_regset *i2c_buf;
 	struct ddb_regset *idma;
@@ -172,6 +172,7 @@ struct ddb_info {
 #define TS_QUIRK_SERIAL    1
 #define TS_QUIRK_REVERSED  2
 #define TS_QUIRK_NO_OUTPUT 4
+	u32 tempmon_irq;
 	struct ddb_regmap *regmap;
 };

@@ -338,10 +339,6 @@ struct mod_base {
 	u32                    frequency;
 	u32                    flat_start;
 	u32                    flat_end;
-
-	spinlock_t             temp_lock;
-	int                    OverTemperatureError;
-	u8                     temp_tab[11];
 };

 struct ddb_mod {
@@ -424,6 +421,10 @@ struct ddb_link {
 	struct ddb_lnb         lnb;
 	struct tasklet_struct  tasklet;
 	struct ddb_ids         ids;
+
+	spinlock_t             temp_lock;
+	int                    OverTemperatureError;
+	u8                     temp_tab[11];
 };

 struct ddb {
@@ -471,6 +472,7 @@ struct ddb {

 	struct mod_base        mod_base;
 	struct ddb_mod         mod[24];
+
 };

 static inline void ddbwriteb(struct ddb *dev, u32 val, u32 adr)
@@ -520,7 +522,7 @@ static inline void gtlw(struct ddb_link *link)
 }
 #endif

-#if 0
+
 static u32 ddblreadl(struct ddb_link *link, u32 adr)
 {
 	if (unlikely(link->nr)) {
@@ -554,7 +556,6 @@ static void ddblwritel(struct ddb_link *link, u32 val, u32 adr)
 	}
 	writel(val, (char *) (link->dev->regs + (adr)));
 }
-#endif

 static u32 ddbreadl(struct ddb *dev, u32 adr)
 {
@@ -744,12 +745,12 @@ struct DDMOD_FLASH {
 int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg);
 int ddbridge_mod_init(struct ddb *dev);
 void ddbridge_mod_output_stop(struct ddb_output *output);
-void ddbridge_mod_output_start(struct ddb_output *output);
+int ddbridge_mod_output_start(struct ddb_output *output);
 void ddbridge_mod_rate_handler(unsigned long data);


 int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len);

-#define DDBRIDGE_VERSION "0.9.24"
+#define DDBRIDGE_VERSION "0.9.25"

 #endif
--- a/frontends/cxd2843.c
+++ b/frontends/cxd2843.c
@@ -1,9 +1,10 @@
 /*
 * Driver for the Sony CXD2843ER DVB-T/T2/C/C2 demodulator.
- * Also supports the CXD2837ER DVB-T/T2/C and the
- * CXD2838ER ISDB-T demodulator.
+ * Also supports the CXD2837ER DVB-T/T2/C, the
+ * CXD2838ER ISDB-T demodulator and the 
+ * CXD2854 DVB-T/T2/C/C2 ISDB-T demodulator.
 *
- * Copyright (C) 2013-2015 Digital Devices GmbH
+ * Copyright (C) 2013-2016 Digital Devices GmbH
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
@@ -42,7 +43,7 @@

 #define USE_ALGO 1

-enum demod_type { CXD2843, CXD2837, CXD2838 };
+enum demod_type { CXD2843, CXD2837, CXD2838, CXD2854 };
 enum demod_state { Unknown, Shutdown, Sleep, ActiveT,
 		   ActiveT2, ActiveC, ActiveC2, ActiveIT };
 enum t2_profile { T2P_Base, T2P_Lite };
@@ -83,16 +84,17 @@ struct cxd_state {

 	unsigned long tune_time;

-	u32   LastBERNominator;
+	u32   LastBERNumerator;
 	u32   LastBERDenominator;
 	u8    BERScaleMax;
+	u8    is2k14;
+	u8    is24MHz;
 };

 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
 {
 	struct i2c_msg msg = {
-		.addr = adr, .flags = 0, .buf = data, .len = len};
-
+		.addr = adr, .flags = 0, .buf = data, .len = len}; 
 	if (i2c_transfer(adap, &msg, 1) != 1) {
 		pr_err("cxd2843: i2c_write error\n");
 		return -1;
@@ -409,7 +411,8 @@ static void Active_to_Sleep(struct cxd_state *state)
 	writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */
 	writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */
 	writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */
-	writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */
+	writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
+	writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
 	writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */
 	state->state = Sleep;
 }
@@ -432,7 +435,42 @@ static void ActiveT2_to_Sleep(struct cxd_state *state)
 	writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */
 	writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */
 	writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */
-	writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */
+	writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
+	writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
+	writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */
+	state->state = Sleep;
+}
+
+static void ActiveIT_to_Sleep(struct cxd_state *state)
+{
+	if (state->state <= Sleep)
+		return;
+
+	writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS */
+	writeregt(state, 0x00, 0x80, 0x3F); /* Enable HighZ 1 */
+	writeregt(state, 0x00, 0x81, 0xFF); /* Enable HighZ 2 */
+
+	if (state->is2k14) {
+		writebitst(state, 0x10, 0x69, 0x05, 0x07);
+		writebitst(state, 0x10, 0x6b, 0x07, 0x07);
+		writebitst(state, 0x10, 0x9d, 0x14, 0xff);
+		writebitst(state, 0x10, 0xd3, 0x00, 0x1f);
+		writebitst(state, 0x10, 0xed, 0x01, 0x01);
+		writebitst(state, 0x10, 0xe2, 0x4e, 0x80);
+		writebitst(state, 0x10, 0xf2, 0x03, 0x10);
+		writebitst(state, 0x10, 0xde, 0x32, 0x3f);
+
+		writebitst(state, 0x15, 0xde, 0x03, 0x03);
+		writebitst(state, 0x1e, 0x73, 0x00, 0xff);
+		writebitst(state, 0x63, 0x81, 0x01, 0x01);
+	}
+	
+	writeregx(state, 0x00, 0x18, 0x01); /* Disable ADC 4 */
+	writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */
+	writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */
+	writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */
+	writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
+	writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
 	writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */
 	state->state = Sleep;
 }
@@ -478,7 +516,8 @@ static void ActiveC2_to_Sleep(struct cxd_state *state)
 	writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */
 	writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */
 	writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */
-	writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */
+	writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
+	writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
 	writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */
 	state->state = Sleep;
 }
@@ -582,7 +621,8 @@ static void Sleep_to_ActiveT(struct cxd_state *state, u32 iffreq)
 	ConfigureTS(state, ActiveT);
 	writeregx(state, 0x00, 0x17, 0x01);   /* Mode */
 	writeregt(state, 0x00, 0x2C, 0x01);   /* Demod Clock */
-	writeregt(state, 0x00, 0x2F, 0x00);   /* Disable RF Monitor */
+	writeregt(state, 0x00, 0x59, 0x00);   /* Disable RF Monitor ADC */
+	writeregt(state, 0x00, 0x2F, 0x00);   /* Disable RF Monitor Clock */
 	writeregt(state, 0x00, 0x30, 0x00);   /* Enable ADC Clock */
 	writeregt(state, 0x00, 0x41, 0x1A);   /* Enable ADC1 */
 	{
@@ -678,7 +718,8 @@ static void Sleep_to_ActiveT2(struct cxd_state *state, u32 iffreq)

 	writeregx(state, 0x00, 0x17, 0x02);   /* Mode */
 	writeregt(state, 0x00, 0x2C, 0x01);   /* Demod Clock */
-	writeregt(state, 0x00, 0x2F, 0x00);   /* Disable RF Monitor */
+	writeregt(state, 0x00, 0x59, 0x00);   /* Disable RF Monitor ADC */
+	writeregt(state, 0x00, 0x2F, 0x00);   /* Disable RF Monitor Clock */
 	writeregt(state, 0x00, 0x30, 0x00);   /* Enable ADC Clock */
 	writeregt(state, 0x00, 0x41, 0x1A);   /* Enable ADC1 */

@@ -730,7 +771,8 @@ static void Sleep_to_ActiveC(struct cxd_state *state, u32 iffreq)

 	writeregx(state, 0x00, 0x17, 0x04);   /* Mode */
 	writeregt(state, 0x00, 0x2C, 0x01);   /* Demod Clock */
-	writeregt(state, 0x00, 0x2F, 0x00);   /* Disable RF Monitor */
+	writeregt(state, 0x00, 0x59, 0x00);   /* Disable RF Monitor ADC */
+	writeregt(state, 0x00, 0x2F, 0x00);   /* Disable RF Monitor Clock */
 	writeregt(state, 0x00, 0x30, 0x00);   /* Enable ADC Clock */
 	writeregt(state, 0x00, 0x41, 0x1A);   /* Enable ADC1 */

@@ -801,7 +843,8 @@ static void Sleep_to_ActiveC2(struct cxd_state *state, u32 iffreq)

 	writeregx(state, 0x00, 0x17, 0x05);   /* Mode */
 	writeregt(state, 0x00, 0x2C, 0x01);   /* Demod Clock */
-	writeregt(state, 0x00, 0x2F, 0x00);   /* Disable RF Monitor */
+	writeregt(state, 0x00, 0x59, 0x00);   /* Disable RF Monitor ADC */
+	writeregt(state, 0x00, 0x2F, 0x00);   /* Disable RF Monitor Clock */
 	writeregt(state, 0x00, 0x30, 0x00);   /* Enable ADC Clock */
 	writeregt(state, 0x00, 0x41, 0x1A);   /* Enable ADC1 */

@@ -873,9 +916,12 @@ static void BandSettingIT(struct cxd_state *state, u32 iffreq)
 		/* Add EQ Optimisation for tuner here */
 		writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data));

-		writeregt(state, 0x10, 0xD7, 0x00);   /* System Bandwidth */
+		writebitst(state, 0x10, 0xD7, 0x00, 0x07); /* System Bandwidth */
 		/*u8 CL_data[] = { 0x13, 0xFC }; */
 		writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data));
+
+		writebitst(state, 0x12, 0x71, 0x03, 0x07);
+		writeregt(state, 0x15, 0xbe, 0x03);
 	}
 	break;
 	case 7:
@@ -887,22 +933,35 @@ static void BandSettingIT(struct cxd_state *state, u32 iffreq)
 		writeregst(state, 0x10, 0x9F, TR_data, sizeof(TR_data));
 		writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data));

-		writeregt(state, 0x10, 0xD7, 0x02);
+		writebitst(state, 0x10, 0xD7, 0x02, 0x07);
 		/*static u8 CL_data[] = { 0x1A, 0xFA };*/
 		writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data));
+
+		writebitst(state, 0x12, 0x71, 0x03, 0x07);
+		writeregt(state, 0x15, 0xbe, 0x02);
 	}
 	break;
 	case 6:
 	{
 		u8 TR_data[] = { 0x14, 0x2E, 0x00, 0x00, 0x00 };
-		u8 CL_data[] = { 0x1F, 0xEC };
 		/*u8 TR_data[] = { 0x17, 0xA0, 0x00, 0x00, 0x00 }; */
 		/*u8 CL_data[] = { 0x1F, 0x79 }; */

 		writeregst(state, 0x10, 0x9F, TR_data, sizeof(TR_data));
 		writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data));
-		writeregt(state, 0x10, 0xD7, 0x04);
-		writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data));
+		writebitst(state, 0x10, 0xD7, 0x04, 0x07);
+
+		if (state->is2k14) {
+			u8 CL_data[] = { 0x1a, 0xe2 };
+			
+			writeregst(state, 0x10, 0xDd9, CL_data, sizeof(CL_data));
+		} else {
+			u8 CL_data[] = { 0x1F, 0xec };
+			
+			writeregst(state, 0x10, 0xd9, CL_data, sizeof(CL_data));
+		}
+		writebitst(state, 0x12, 0x71, 0x07, 0x07);
+		writeregt(state, 0x15, 0xbe, 0x02);
 	}
 	break;
 	}
@@ -919,8 +978,13 @@ static void Sleep_to_ActiveIT(struct cxd_state *state, u32 iffreq)
 	ConfigureTS(state, ActiveIT);

 	/* writeregx(state, 0x00,0x17,0x01); */  /* 2838 has only one Mode */
+	if (state->is2k14)
+		writeregx(state, 0x00, 0x17, 0x06);
 	writeregt(state, 0x00, 0x2C, 0x01);   /* Demod Clock */
-	writeregt(state, 0x00, 0x2F, 0x00);   /* Disable RF Monitor */
+	if (state->is2k14) {
+		writeregt(state, 0x00, 0x59, 0x00);   /* Disable RF Monitor ADC */
+		writeregt(state, 0x00, 0x2F, 0x00);   /* Disable RF Monitor Clock */
+	}
 	writeregt(state, 0x00, 0x30, 0x00);   /* Enable ADC Clock */
 	writeregt(state, 0x00, 0x41, 0x1A);   /* Enable ADC1 */

@@ -932,13 +996,43 @@ static void Sleep_to_ActiveIT(struct cxd_state *state, u32 iffreq)
 	}
 	writeregx(state, 0x00, 0x18, 0x00);   /* Enable ADC 4 */

-	writeregst(state, 0x60, 0xA8, data2, sizeof(data2));
+	
+	if (state->is2k14) {
+		writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */

+		writebitst(state, 0x18, 0x30, 0x01, 0x01);
+		writebitst(state, 0x18, 0x31, 0x00, 0x01);
+		writebitst(state, 0x00, 0xce, 0x00, 0x01);
+		writebitst(state, 0x00, 0xcf, 0x00, 0x01);
+
+		writebitst(state, 0x10, 0x69, 0x04, 0x07);
+		writebitst(state, 0x10, 0x6b, 0x03, 0x07);
+		writebitst(state, 0x10, 0x9d, 0x50, 0xff);
+		writebitst(state, 0x10, 0xd3, 0x06, 0x1f);
+		writebitst(state, 0x10, 0xed, 0x00, 0x01);
+		writebitst(state, 0x10, 0xe2, 0xce, 0x80);
+		writebitst(state, 0x10, 0xf2, 0x13, 0x10);
+		writebitst(state, 0x10, 0xde, 0x2e, 0x3f);
+
+		writebitst(state, 0x15, 0xde, 0x02, 0x03);
+		writebitst(state, 0x1e, 0x73, 0x68, 0xff);
+		writebitst(state, 0x63, 0x81, 0x00, 0x01);
+	}
+        //if( m_is24MHz )
+        //{
+        //    static BYTE TSIF_data[2] = { 0x60,0x00 } ; // 24 MHz
+        //    CHK_ERROR(WriteRegT(0x10,0xBF,TSIF_data,sizeof(TSIF_data)));
+        //    static BYTE data[3] = { 0xB7,0x1B,0x00 };  // 24 MHz
+        //    CHK_ERROR(WriteRegT(0x60,0xA8,data,sizeof(data)));
+        //}
+        //else
 	writeregst(state, 0x10, 0xBF, TSIF_data, sizeof(TSIF_data));
-
-	writeregt(state, 0x10, 0xE2, 0xCE); /* OREG_PNC_DISABLE */
-	writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */
-
+	writeregst(state, 0x60, 0xa8, data2, sizeof(data2));
+	
+	if (!state->is2k14) {
+		writeregt(state, 0x10, 0xE2, 0xCE); /* OREG_PNC_DISABLE */
+		writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */
+	}
 	BandSettingIT(state, iffreq);

 	writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */
@@ -1046,6 +1140,9 @@ static void ShutDown(struct cxd_state *state)
 	case ActiveC2:
 		ActiveC2_to_Sleep(state);
 		break;
+	case ActiveIT:
+		ActiveIT_to_Sleep(state);
+		break;
 	default:
 		Active_to_Sleep(state);
 		break;
@@ -1105,12 +1202,14 @@ static int Start(struct cxd_state *state, u32 IntermediateFrequency)
 		newDemodState = ActiveC;
 		break;
 	case OM_DVBC2:
-		if (state->type != CXD2843)
+		if (state->type != CXD2843 && state->type != CXD2854)
 			return -EINVAL;
 		newDemodState = ActiveC2;
 		break;
 	case OM_ISDBT:
-		if (state->type != CXD2838)
+		if (state->type != CXD2838 && state->type != CXD2854)
+			return -EINVAL;
+		if (state->type == CXD2854 && !state->is24MHz && state->bw != 6)
 			return -EINVAL;
 		newDemodState = ActiveIT;
 		break;
@@ -1123,7 +1222,7 @@ static int Start(struct cxd_state *state, u32 IntermediateFrequency)
 	state->L1PostTimeout = 0;
 	state->last_status = 0;
 	state->FirstTimeLock = 1;
-	state->LastBERNominator = 0;
+	state->LastBERNumerator = 0;
 	state->LastBERDenominator = 1;
 	state->BERScaleMax = 19;

@@ -1165,6 +1264,9 @@ static int Start(struct cxd_state *state, u32 IntermediateFrequency)
 			case ActiveC2:
 				ActiveC2_to_Sleep(state);
 				break;
+			case ActiveIT:
+				ActiveIT_to_Sleep(state);
+				break;
 			default:
 				Active_to_Sleep(state);
 				break;
@@ -1474,16 +1576,16 @@ static int get_ber_t(struct cxd_state *state, u32 *n, u32 *d)
 	Scale &= 0x1F;

 	if (BERRegs[0] & 0x80) {
-		state->LastBERNominator = (((u32) BERRegs[0] & 0x3F) << 16) |
+		state->LastBERNumerator = (((u32) BERRegs[0] & 0x3F) << 16) |
 			(((u32) BERRegs[1]) << 8) | BERRegs[2];
 		state->LastBERDenominator = 1632 << Scale;
-		if (state->LastBERNominator < 256 &&
+		if (state->LastBERNumerator < 256 &&
 		    Scale < state->BERScaleMax) {
 			writebitst(state, 0x10, 0x60, Scale + 1, 0x1F);
-		} else if (state->LastBERNominator > 512 && Scale > 11)
+		} else if (state->LastBERNumerator > 512 && Scale > 11)
 			writebitst(state, 0x10, 0x60, Scale - 1, 0x1F);
 	}
-	*n = state->LastBERNominator;
+	*n = state->LastBERNumerator;
 	*d = state->LastBERDenominator;

 	return 0;
@@ -1504,9 +1606,9 @@ static int get_ber_t2(struct cxd_state *state, u32 *n, u32 *d)
 	*n = 0;
 	*d = 1;
 	freeze_regst(state);
-	readregst(state, 0x24, 0x40, BERRegs, 4);
-	readregst(state, 0x22, 0x5e, &FECType, 1);
-	readregst(state, 0x22, 0x5b, &CodeRate, 1);
+	readregst_unlocked(state, 0x24, 0x40, BERRegs, 4);
+	readregst_unlocked(state, 0x22, 0x5e, &FECType, 1);
+	readregst_unlocked(state, 0x22, 0x5b, &CodeRate, 1);

 	FECType &= 0x03;
 	CodeRate &= 0x07;
@@ -1517,17 +1619,17 @@ static int get_ber_t2(struct cxd_state *state, u32 *n, u32 *d)

 	readregst(state, 0x20, 0x72, &Scale, 1);
 	Scale &= 0x0F;
-        if (BERRegs[0] & 0x01) {
-		state->LastBERNominator = (((u32) BERRegs[1] & 0x3F) << 16) |
+	if (BERRegs[0] & 0x01) {
+		state->LastBERNumerator = (((u32) BERRegs[1] & 0x3F) << 16) |
 			(((u32) BERRegs[2]) << 8) | BERRegs[3];
 		state->LastBERDenominator = nBCHBitsLookup[FECType][CodeRate] << Scale;
-		if (state->LastBERNominator < 256 &&
+		if (state->LastBERNumerator < 256 &&
 		    Scale < state->BERScaleMax) {
 			writebitst(state, 0x20, 0x72, Scale + 1, 0x0F);
-		} else if (state->LastBERNominator > 512 && Scale > 8)
+		} else if (state->LastBERNumerator > 512 && Scale > 8)
 			writebitst(state, 0x20, 0x72, Scale - 1, 0x0F);
 	}
-	*n = state->LastBERNominator;
+	*n = state->LastBERNumerator;
 	*d = state->LastBERDenominator;
 	return 0;
 }
@@ -1545,16 +1647,16 @@ static int get_ber_c(struct cxd_state *state, u32 *n, u32 *d)
 	Scale &= 0x1F;

 	if (BERRegs[0] & 0x80) {
-		state->LastBERNominator = (((u32) BERRegs[0] & 0x3F) << 16) |
+		state->LastBERNumerator = (((u32) BERRegs[0] & 0x3F) << 16) |
 			(((u32) BERRegs[1]) << 8) | BERRegs[2];
 		state->LastBERDenominator = 1632 << Scale;
-		if (state->LastBERNominator < 256 &&
+		if (state->LastBERNumerator < 256 &&
 		    Scale < state->BERScaleMax) {
 			writebitst(state, 0x40, 0x60, Scale + 1, 0x1F);
-		} else if (state->LastBERNominator > 512 && Scale > 11)
+		} else if (state->LastBERNumerator > 512 && Scale > 11)
 			writebitst(state, 0x40, 0x60, Scale - 1, 0x1F);
 	}
-	*n = state->LastBERNominator;
+	*n = state->LastBERNumerator;
 	*d = state->LastBERDenominator;

 	return 0;
@@ -2152,6 +2254,39 @@ static int get_frontend(struct dvb_frontend *fe)
 	return 0;
 }

+static struct dvb_frontend_ops common_ops_2854 = {
+	.delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2, SYS_DVBC2, SYS_ISDBT },
+	.info = {
+		.name = "CXD2854 DVB-C/C2 DVB-T/T2 ISDB-T",
+		.frequency_stepsize = 166667,	/* DVB-T only */
+		.frequency_min = 47000000,	/* DVB-T: 47125000 */
+		.frequency_max = 865000000,	/* DVB-C: 862000000 */
+		.symbol_rate_min = 870000,
+		.symbol_rate_max = 11700000,
+		.caps = FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 |
+		        FE_CAN_QAM_64 | FE_CAN_QAM_128 | FE_CAN_QAM_256 |
+		        FE_CAN_QAM_AUTO | 
+			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+			FE_CAN_FEC_4_5 |
+			FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+			FE_CAN_TRANSMISSION_MODE_AUTO |
+			FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO |
+			FE_CAN_RECOVER | FE_CAN_MUTE_TS | FE_CAN_2G_MODULATION
+	},
+	.release = release,
+	.sleep = sleep,
+	.i2c_gate_ctrl = gate_ctrl,
+	.set_frontend = set_parameters,
+
+	.get_tune_settings = get_tune_settings,
+	.read_status = read_status,
+	.read_ber = read_ber,
+	.read_signal_strength = read_signal_strength,
+	.read_snr = read_snr,
+	.read_ucblocks = read_ucblocks,
+	.get_frontend = get_frontend,
+};
+
 static struct dvb_frontend_ops common_ops_2843 = {
 	.delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2, SYS_DVBC2 },
 	.info = {
@@ -2292,6 +2427,12 @@ static int probe(struct cxd_state *state)
 		memcpy(&state->frontend.ops, &common_ops_2838,
 		       sizeof(struct dvb_frontend_ops));
 		break;
+	case 0xc1:
+		state->type = CXD2854;
+		memcpy(&state->frontend.ops, &common_ops_2854,
+		       sizeof(struct dvb_frontend_ops));
+		state->is2k14 = 1;
+		break;
 	default:
 		return -1;
 	}
--- a/frontends/stv090x.c
+++ b/frontends/stv090x.c
@@ -5144,69 +5144,6 @@ static int stv090x_get_frontend(struct dvb_frontend *fe)
 	return 0;
 }

-static int get_frontend(struct dvb_frontend *fe)
-{
-	struct stv090x_state *state = fe->demodulator_priv;
-	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
-	u8 tmp;
-	u32 reg = 0;
-	
-	if (state->rec_mode == 2) {
-		u32 mc;
-		enum fe_modulation modcod2mod[0x20] = {
-			QPSK, QPSK, QPSK, QPSK,
-			QPSK, QPSK, QPSK, QPSK,
-			QPSK, QPSK, QPSK, QPSK,
-			PSK_8, PSK_8, PSK_8, PSK_8,
-			PSK_8, PSK_8, APSK_16, APSK_16,
-			APSK_16, APSK_16, APSK_16, APSK_16,
-			APSK_32, APSK_32, APSK_32, APSK_32,
-			APSK_32, 
-		};
-		enum fe_code_rate modcod2fec[0x20] = {
-			FEC_NONE, FEC_1_4, FEC_1_3, FEC_2_5,
-			FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
-			FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
-			FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
-			FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
-			FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
-			FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
-			FEC_9_10
-		};		
-		mc = state->modcod;
-		p->pilot = (state->pilots & 0x01) ? PILOT_ON : PILOT_OFF;
-		p->modulation = modcod2mod[mc];
-		p->fec_inner = modcod2fec[mc];	
-        } else if (state->rec_mode == 1) {
-		reg = STV090x_READ_DEMOD(state, VITCURPUN);
-		switch( reg & 0x1F ) {
-                case 0x0d:
-			p->fec_inner = FEC_1_2;
-			break;
-                case 0x12:
-			p->fec_inner = FEC_2_3;
-			break;
-                case 0x15:
-			p->fec_inner = FEC_3_4;
-			break;
-                case 0x18:
-			p->fec_inner = FEC_5_6;
-			break;
-                case 0x1a:
-			p->fec_inner = FEC_7_8;
-			break;
-		default:
-			p->fec_inner = FEC_NONE;
-			break;
-		}
-		p->rolloff = ROLLOFF_35;
-	} else {
-		
-	}
-	
-	return 0;
-}
-
 static struct dvb_frontend_ops stv090x_ops = {
 #ifndef USE_API3
        .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
--- a/frontends/stv0910.c
+++ b/frontends/stv0910.c
@@ -1139,6 +1139,9 @@ static int probe(struct stv *state)
 	write_reg(state, RSTV0910_CFGEXT,    0x02);  /* CFGEXT */
 	write_reg(state, RSTV0910_GENCFG,    0x15);  /* GENCFG */

+	write_reg(state, RSTV0910_P1_TNRCFG2, 0x02);  /* IQSWAP = 0 */
+	write_reg(state, RSTV0910_P2_TNRCFG2, 0x82);  /* IQSWAP = 1 */
+
 	write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
 	write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
 	write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
@@ -1251,7 +1254,7 @@ static int get_frequency_offset(struct stv *state, s32 *off)
 	derot = ((u32) cfr2 << 16) | ((u32)cfr1 << 8) | cfr0;
 	if (derot & (1<<23))
 		derot |= 0xFF000000;
-        *off = - (s32) (((s64) derot * (s64) state->base->mclk) >> 24);
+        *off = (s32) (((s64) derot * (s64) state->base->mclk) >> 24);
 	//pr_info("foff = %d\n", *off);
 	return 0;
 }
Author	SHA1	Message	Date
mvoelkel	7db462ca68	Merge branch 'master' into internal	2016-08-31 22:25:54 +02:00
mvoelkel	cd229fabf5	stv090x: removed duplicate function	2016-08-31 22:24:37 +02:00
mvoelkel	5252c5318d	Version 0.9.25	2016-08-31 19:10:39 +02:00
mvoelkel	95b9a644b6	Fix dead lock in T2 BER thanks to Andrey Dyldin (cesbo) for heads up	2016-08-31 19:10:23 +02:00
mvoelkel	4f452819df	Set input IQ swap to match hardware, fiexes sign issue with offset	2016-08-31 18:46:07 +02:00
Ralph Metzler	f20b16cd12	check if info exists	2016-08-29 21:13:48 +02:00
Ralph Metzler	1f4ae2bd51	- add support for new Max S8/A8 with temperature monitor - move temperature monitor code from mod to core and cleanup modulator ioctls	2016-08-29 18:44:53 +02:00
Ralph Metzler	2ec7863b04	add support for cxd2854 (not for dvb-s/s2)	2016-08-29 18:37:47 +02:00
Ralph Metzler	fb022009ee	support new cards	2016-08-29 18:35:40 +02:00
Ralph Metzler	a98a7c95a8	fix for V2	2016-08-04 19:40:55 +02:00