frodovdr/dddvb
1
0
Fork 0
mirror of https://github.com/DigitalDevices/dddvb.git synced 2025-03-01 10:35:23 +00:00
Code Issues Packages Projects Releases Wiki Activity

Compare commits

base: frodovdr:0.9.24
Branches Tags
frodovdr:master frodovdr:internal
frodovdr:0.9.40a frodovdr:0.9.40 frodovdr:0.9.39 frodovdr:0.9.38 frodovdr:0.9.38-pre.6 frodovdr:0.9.38-pre.5 frodovdr:0.9.38-pre.4 frodovdr:0.9.38pre3 frodovdr:0.9.38pre2 frodovdr:0.9.38pre1 frodovdr:0.9.37 frodovdr:0.9.36 frodovdr:0.9.35 frodovdr:0.9.34 frodovdr:0.9.33 frodovdr:0.9.32-compile-fix frodovdr:0.9.32 frodovdr:0.9.31-intermediate frodovdr:0.9.30-intermediate frodovdr:0.9.29 frodovdr:0.9.28-v7a frodovdr:0.9.28 frodovdr:0.9.26 frodovdr:0.9.25 frodovdr:0.9.24 frodovdr:0.9.23 frodovdr:0.9.22 frodovdr:0.9.21 frodovdr:0.9.20 frodovdr:0.9.19c
..
compare: frodovdr:0.9.28-v7a
Branches Tags
frodovdr:master frodovdr:internal
frodovdr:0.9.40a frodovdr:0.9.40 frodovdr:0.9.39 frodovdr:0.9.38 frodovdr:0.9.38-pre.6 frodovdr:0.9.38-pre.5 frodovdr:0.9.38-pre.4 frodovdr:0.9.38pre3 frodovdr:0.9.38pre2 frodovdr:0.9.38pre1 frodovdr:0.9.37 frodovdr:0.9.36 frodovdr:0.9.35 frodovdr:0.9.34 frodovdr:0.9.33 frodovdr:0.9.32-compile-fix frodovdr:0.9.32 frodovdr:0.9.31-intermediate frodovdr:0.9.30-intermediate frodovdr:0.9.29 frodovdr:0.9.28-v7a frodovdr:0.9.28 frodovdr:0.9.26 frodovdr:0.9.25 frodovdr:0.9.24 frodovdr:0.9.23 frodovdr:0.9.22 frodovdr:0.9.21 frodovdr:0.9.20 frodovdr:0.9.19c

34 Commits
0.9.24 ... 0.9.28-v7a

Author SHA1 Message Date
Ralph Metzler
37de742aad add id for pro advanced 2017-02-06 13:28:45 +01:00
Ralph Metzler
1e99122d52 support cine s2 v7a 2017-02-06 12:49:16 +01:00
Ralph Metzler
cd5de95023 fix error handling and ID output length 2017-02-06 12:48:54 +01:00
Ralph Metzler
c56f593a4c add support for single demod mode for testing high bit rates 2017-02-06 12:48:48 +01:00
Ralph Metzler
1f77192d62 mask lower bits for temp 2016-12-14 19:24:58 +01:00
Ralph Metzler
fc4a807b4e add support for new cine and change 24 MHz osciallator handling 2016-12-14 19:11:57 +01:00
Ralph Metzler
b6d5976e14 support for 24MHz crystals 2016-11-07 21:19:53 +01:00
Ralph Metzler
101289c77e move common flash code to flash.c 2016-10-24 15:15:09 +02:00
Ralph Metzler
26eedb3d26 change some pr_info to pr_debug 2016-10-24 15:13:26 +02:00
Ralph Metzler
d1387078f1 add DDBridge to all message lines 2016-10-10 00:19:16 +02:00
Ralph Metzler
6bf258b54c - initialize SKU ids 
- add debug code to check if firmware crashed
 2016-10-10 00:18:37 +02:00
Ralph Metzler
4435efeab5 - initialize SNR values to 0 
- check for 0 in register values so that log function does not throw kernel warnings
 2016-10-10 00:16:10 +02:00
Ralph Metzler
633797e05f add setmod2 2016-10-10 00:14:38 +02:00
Ralph Metzler
4ee27ff317 change DMA buf size for small bufs to be multiple of 128 2016-10-10 00:14:03 +02:00
Ralph Metzler
7d7da35fb5 add optional file name for flashread 2016-10-10 00:12:47 +02:00
Ralph Metzler
a3b517391a use device id instead of type 2016-10-10 00:10:39 +02:00
Ralph Metzler
1171b345df change MOD_ to MODULATOR_ because of overlapwith timex.h 2016-09-12 14:41:47 +02:00
Ralph Metzler
7f746f0219 backwards compatibility: set all frequencies of V2 card if base frequency is set 2016-09-12 13:46:10 +02:00
mvoelkel
49a05e75af Set version 0.9.26 2016-09-05 16:16:02 +02:00
Ralph Metzler
c546918e79 set deafult ci bitrate to 70MHz 2016-09-05 14:25:43 +02:00
Ralph Metzler
570a565f37 add test app for new modulator API 2016-09-05 14:25:43 +02:00
Ralph Metzler
85b1447059 add new properties API for modulator 2016-09-05 14:25:43 +02:00
Ralph Metzler
a4c275895d missing init for status 2016-09-05 14:25:43 +02:00
Ralph Metzler
7a8d3f80c4 add modulator properties 2016-09-05 14:25:43 +02:00
mvoelkel
7db462ca68 Merge branch 'master' into internal 2016-08-31 22:25:54 +02:00
mvoelkel
cd229fabf5 stv090x: removed duplicate function 2016-08-31 22:24:37 +02:00
mvoelkel
5252c5318d Version 0.9.25 2016-08-31 19:10:39 +02:00
mvoelkel
95b9a644b6 Fix dead lock in T2 BER 
thanks to Andrey Dyldin (cesbo) for heads up
 2016-08-31 19:10:23 +02:00
mvoelkel
4f452819df Set input IQ swap to match hardware, fiexes sign issue with offset 2016-08-31 18:46:07 +02:00
Ralph Metzler
f20b16cd12 check if info exists 2016-08-29 21:13:48 +02:00
Ralph Metzler
1f4ae2bd51 - add support for new Max S8/A8 with temperature monitor 
- move temperature monitor code from mod to core and cleanup modulator ioctls
 2016-08-29 18:44:53 +02:00
Ralph Metzler
2ec7863b04 add support for cxd2854 (not for dvb-s/s2) 2016-08-29 18:37:47 +02:00
Ralph Metzler
fb022009ee support new cards 2016-08-29 18:35:40 +02:00
Ralph Metzler
a98a7c95a8 fix for V2 2016-08-04 19:40:55 +02:00
23 changed files with 1971 additions and 1693 deletions
Expand all files Collapse all files

5
apps/Makefile
View File

@@ -1,4 +1,4 @@
all: cit citin flashprog modt ddtest setmod ddflash
all: cit citin flashprog modt ddtest setmod ddflash setmod2
cit: cit.c
gcc -o cit cit.c -lpthread
@@ -9,6 +9,9 @@ modt: modt.c
setmod: setmod.c
gcc -o setmod setmod.c -I../include/
setmod2: setmod2.c
gcc -o setmod2 setmod2.c -I../include/
flashprog: flashprog.c
gcc -o flashprog flashprog.c

1
apps/flash.c Symbolic link
View File

@@ -0,0 +1 @@
./octonet/flash.c

488
apps/flashprog.c
View File

@@ -33,379 +33,7 @@
#include <sys/ioctl.h>
#include <linux/types.h>
#define DDB_MAGIC 'd'
static uint32_t linknr = 0;
struct ddb_id {
__u16 vendor;
__u16 device;
__u16 subvendor;
__u16 subdevice;
__u32 hw;
__u32 regmap;
};
struct ddb_flashio {
__u8 *write_buf;
__u32 write_len;
__u8 *read_buf;
__u32 read_len;
__u32 link;
};
#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio)
#define IOCTL_DDB_ID _IOR(DDB_MAGIC, 0x03, struct ddb_id)
int flashio(int ddb, uint8_t *wbuf, uint32_t wlen, uint8_t *rbuf, uint32_t rlen)
{
struct ddb_flashio fio = {
.write_buf=wbuf,
.write_len=wlen,
.read_buf=rbuf,
.read_len=rlen,
.link=linknr,
};
return ioctl(ddb, IOCTL_DDB_FLASHIO, &fio);
}
enum {
UNKNOWN_FLASH = 0,
ATMEL_AT45DB642D = 1,
SSTI_SST25VF016B = 2,
SSTI_SST25VF032B = 3,
SSTI_SST25VF064C = 4,
SPANSION_S25FL116K = 5,
};
int flashread(int ddb, uint8_t *buf, uint32_t addr, uint32_t len)
{
uint8_t cmd[4]= {0x03, (addr >> 16) & 0xff,
(addr >> 8) & 0xff, addr & 0xff};
return flashio(ddb, cmd, 4, buf, len);
}
int flashdump(int ddb, uint32_t addr, uint32_t len)
{
int i, j;
uint8_t buf[32];
int bl = sizeof(buf);
for (j=0; j<len; j+=bl, addr+=bl) {
flashread(ddb, buf, addr, bl);
for (i=0; i<bl; i++) {
printf("%02x ", buf[i]);
}
printf("\n");
}
}
int FlashDetect(int dev)
{
uint8_t Cmd = 0x9F;
uint8_t Id[3];
int r = flashio(dev, &Cmd,1,Id,3);
if (r < 0)
return r;
if (Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x41 )
r = SSTI_SST25VF016B;
else if( Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x4A )
r = SSTI_SST25VF032B;
else if( Id[0] == 0x1F && Id[1] == 0x28 )
r = ATMEL_AT45DB642D;
else if( Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x4B )
r = SSTI_SST25VF064C;
else if( Id[0] == 0x01 && Id[1] == 0x40 && Id[2] == 0x15 )
r = SPANSION_S25FL116K;
else
r = UNKNOWN_FLASH;
switch(r) {
case UNKNOWN_FLASH:
printf("Unknown Flash Flash ID = %02x %02x %02x\n",Id[0],Id[1],Id[2]);
break;
case ATMEL_AT45DB642D:
printf("Flash: Atmel AT45DB642D 64 MBit\n");
break;
case SSTI_SST25VF016B:
printf("Flash: SSTI SST25VF016B 16 MBit\n");
break;
case SSTI_SST25VF032B:
printf("Flash: SSTI SST25VF032B 32 MBit\n"); break;
case SSTI_SST25VF064C:
printf("Flash: SSTI SST25VF064C 64 MBit\n"); break;
case SPANSION_S25FL116K:
printf("Flash: SPANSION S25FL116K 16 MBit\n"); break;
}
return r;
}
int FlashWriteAtmel(int dev,uint32_t FlashOffset, uint8_t *Buffer,int BufferSize)
{
int err = 0;
int BlockErase = BufferSize >= 8192;
int i;
if (BlockErase) {
for(i = 0; i < BufferSize; i += 8192 ) {
uint8_t Cmd[4];
if( (i & 0xFFFF) == 0 )
printf(" Erase %08x\n",FlashOffset + i);
Cmd[0] = 0x50; // Block Erase
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = flashio(dev,Cmd,4,NULL,0);
if( err < 0 ) break;
while( 1 )
{
Cmd[0] = 0xD7; // Read Status register
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x80) == 0x80 ) break;
}
}
}
for(i = 0; i < BufferSize; i += 1024 )
{
uint8_t Cmd[4 + 1024];
if( (i & 0xFFFF) == 0 )
{
printf(" Program %08x\n",FlashOffset + i);
}
Cmd[0] = 0x84; // Buffer 1
Cmd[1] = 0x00;
Cmd[2] = 0x00;
Cmd[3] = 0x00;
memcpy(&Cmd[4],&Buffer[i],1024);
err = flashio(dev,Cmd,4 + 1024,NULL,0);
if( err < 0 ) break;
Cmd[0] = BlockErase ? 0x88 : 0x83; // Buffer to Main Memory (with Erase)
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = flashio(dev,Cmd,4,NULL,0);
if( err < 0 ) break;
while( 1 )
{
Cmd[0] = 0xD7; // Read Status register
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x80) == 0x80 ) break;
}
if( err < 0 ) break;
}
return err;
}
int FlashWritePageMode(int dev, uint32_t FlashOffset, uint8_t *Buffer, int BufferSize, uint8_t LockBits)
{
int err = 0, i, j;
uint8_t Cmd[260];
if( (BufferSize % 4096) != 0 )
return -1; // Must be multiple of sector size
do {
Cmd[0] = 0x50; // EWSR
err = flashio(dev, Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x00; // BPx = 0, Unlock all blocks
err = flashio(dev, Cmd,2,NULL,0);
if( err < 0 ) break;
for(i = 0; i < BufferSize; i += 4096 ) {
if( (i & 0xFFFF) == 0 ) {
printf(" Erase %08x\n",FlashOffset + i);
}
Cmd[0] = 0x06; // WREN
err = flashio(dev, Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x20; // Sector erase ( 4Kb)
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = flashio(dev, Cmd,4,NULL,0);
if( err < 0 ) break;
while(1)
{
Cmd[0] = 0x05; // RDRS
err = flashio(dev, Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 ) break;
for (j = BufferSize - 256; j >= 0; j -= 256 )
{
if( (j & 0xFFFF) == 0 )
{
printf(" Programm %08x\n",FlashOffset + j);
}
Cmd[0] = 0x06; // WREN
err = flashio(dev, Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x02; // PP
Cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF );
Cmd[3] = 0x00;
memcpy(&Cmd[4],&Buffer[j],256);
err = flashio(dev, Cmd,260,NULL,0);
if( err < 0 ) break;
while(1)
{
Cmd[0] = 0x05; // RDRS
err = flashio(dev, Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 ) break;
Cmd[0] = 0x50; // EWSR
err = flashio(dev, Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = LockBits; // BPx = 0, Lock all blocks
err = flashio(dev, Cmd,2,NULL,0);
} while(0);
return err;
}
int FlashWriteSSTI_B(int dev, uint32_t FlashOffset, uint8_t *Buffer, int BufferSize)
{
int err = 0;
uint8_t Cmd[6];
int i, j;
// Must be multiple of sector size
if( (BufferSize % 4096) != 0 )
return -1;
do {
Cmd[0] = 0x50; // EWSR
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 )
break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x00; // BPx = 0, Unlock all blocks
err = flashio(dev,Cmd,2,NULL,0);
if( err < 0 )
break;
for(i = 0; i < BufferSize; i += 4096 ) {
if( (i & 0xFFFF) == 0 )
printf(" Erase %08x\n",FlashOffset + i);
Cmd[0] = 0x06; // WREN
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 )
break;
Cmd[0] = 0x20; // Sector erase ( 4Kb)
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = flashio(dev,Cmd,4,NULL,0);
if( err < 0 )
break;
while(1) {
Cmd[0] = 0x05; // RDRS
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 )
break;
for(j = BufferSize - 4096; j >= 0; j -= 4096 ) {
if( (j & 0xFFFF) == 0 )
printf(" Program %08x\n",FlashOffset + j);
for(i = 0; i < 4096; i += 2 ) {
if( i == 0 ) {
Cmd[0] = 0x06; // WREN
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 )
break;
Cmd[0] = 0xAD; // AAI
Cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF );
Cmd[3] = 0x00;
Cmd[4] = Buffer[j+i];
Cmd[5] = Buffer[j+i+1];
err = flashio(dev,Cmd,6,NULL,0);
} else {
Cmd[0] = 0xAD; // AAI
Cmd[1] = Buffer[j+i];
Cmd[2] = Buffer[j+i+1];
err = flashio(dev,Cmd,3,NULL,0);
}
if( err < 0 )
break;
while(1) {
Cmd[0] = 0x05; // RDRS
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 ) break;
Cmd[0] = 0x04; // WDIS
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
}
if( err < 0 ) break;
Cmd[0] = 0x50; // EWSR
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x1C; // BPx = 0, Lock all blocks
err = flashio(dev,Cmd,2,NULL,0);
} while(0);
return err;
}
#include "flash.h"
void get_id(int ddb, struct ddb_id *ddbid) {
uint8_t id[4];
@@ -450,8 +78,8 @@ int main(int argc, char **argv)
uint32_t FlashOffset = 0x10000;
int ddb;
int i, err;
int SectorSize=0;
int FlashSize=0;
uint32_t SectorSize=0;
uint32_t FlashSize=0;
int Flash;
uint32_t svid=0, jump=0, dump=0;
@@ -459,6 +87,7 @@ int main(int argc, char **argv)
int ddbnum = 0;
int force = 0;
char *fname = NULL;
while (1) {
int option_index = 0;
@@ -470,12 +99,15 @@ int main(int argc, char **argv)
{0, 0, 0, 0}
};
c = getopt_long(argc, argv,
"d:n:s:o:l:dfhj",
"d:n:s:o:l:dfhjb:",
long_options, &option_index);
if (c==-1)
break;
switch (c) {
case 'b':
fname = optarg;
break;
case 'd':
dump = strtoul(optarg, NULL, 16);
break;
@@ -513,32 +145,7 @@ int main(int argc, char **argv)
printf("Could not open device\n");
return -1;
}
Flash=FlashDetect(ddb);
switch(Flash) {
case ATMEL_AT45DB642D:
SectorSize = 1024;
FlashSize = 0x800000;
break;
case SSTI_SST25VF016B:
SectorSize = 4096;
FlashSize = 0x200000;
break;
case SSTI_SST25VF032B:
SectorSize = 4096;
FlashSize = 0x400000;
break;
case SSTI_SST25VF064C:
SectorSize = 4096;
FlashSize = 0x800000;
break;
case SPANSION_S25FL116K:
SectorSize = 4096;
FlashSize = 0x200000;
break;
default:
return 0;
}
Flash = flashdetect(ddb, &SectorSize, &FlashSize);
get_id(ddb, &ddbid);
#if 1
@@ -553,23 +160,6 @@ int main(int argc, char **argv)
return 0;
}
if (ddbid.device == 0x0011)
type = 1;
if (ddbid.device == 0x0201)
type = 2;
if (ddbid.device == 0x02)
type = 3;
if (ddbid.device == 0x03)
type = 0;
if (ddbid.device == 0x07)
type = 4;
if (ddbid.device == 0x320)
type = 5;
if (ddbid.device == 0x13)
type = 6;
if (ddbid.device == 0x12)
type = 7;
if (!SectorSize)
return 0;
@@ -612,36 +202,52 @@ int main(int argc, char **argv)
} else {
int fh, i;
int fsize;
char *fname;
switch (type) {
case 0:
fname="DVBBridgeV1B_DVBBridgeV1B.bit";
printf("Octopus\n");
break;
case 1:
fname="CIBridgeV1B_CIBridgeV1B.bit";
printf("Octopus CI\n");
break;
case 2:
fname="DVBModulatorV1B_DVBModulatorV1B.bit";
printf("Modulator\n");
break;
case 3:
if (!fname)
switch (ddbid.device) {
case 0x0002:
fname="DVBBridgeV1A_DVBBridgeV1A.bit";
printf("Octopus 35\n");
break;
case 4:
fname="DVBBridgeV2A_DD01_0007_MXL.bit";
case 0x0003:
fname="DVBBridgeV1B_DVBBridgeV1B.bit";
printf("Octopus\n");
break;
case 0x0006:
fname="DVBBridgeV2A_DD01_0006_STD.fpga";
printf("CineS2 V7\n");
break;
case 0x0007:
fname="DVBBridgeV2A_DD01_0007_MXL.fpga";
printf("Octopus 4/8\n");
break;
case 6:
case 0x0008:
fname="DVBBridgeV2A_DD01_0008_CXD.fpga";
printf("Octopus 4/8\n");
break;
case 0x0011:
fname="CIBridgeV1B_CIBridgeV1B.fpga";
printf("Octopus CI\n");
break;
case 0x0012:
fname="DVBBridgeV2B_DD01_0012_STD.fpga";
printf("Octopus CI\n");
break;
case 0x0013:
fname="DVBBridgeV2B_DD01_0013_PRO.fpga";
printf("Octopus PRO\n");
break;
case 7:
fname="DVBBridgeV2B_DD01_0012_STD.fpga";
printf("Octopus CI\n");
case 0x0201:
fname="DVBModulatorV1B_DVBModulatorV1B.bit";
printf("Modulator\n");
break;
case 0x0203:
fname="DVBModulatorV1B_DD01_0203.fpga";
printf("Modulator Test\n");
break;
case 0x0210:
fname="DVBModulatorV2A_DD01_0210.fpga";
printf("Modulator V2\n");
break;
default:
printf("UNKNOWN\n");
@@ -649,7 +255,7 @@ int main(int argc, char **argv)
}
fh = open(fname, O_RDONLY);
if (fh < 0 ) {
printf("File not found \n");
printf("File %s not found \n", fname);
return 0;
}
printf("Using bitstream %s\n", fname);

247
apps/octonet/ddflash.c
View File

@@ -58,7 +58,6 @@ static int reboot(uint32_t off)
struct ddflash {
int fd;
struct ddb_id id;
uint32_t type;
uint32_t version;
uint32_t flash_type;
@@ -68,74 +67,9 @@ struct ddflash {
uint32_t bufsize;
uint32_t block_erase;
uint8_t * buffer;
uint8_t *buffer;
};
int flashio(int ddb, uint8_t *wbuf, uint32_t wlen, uint8_t *rbuf, uint32_t rlen)
{
struct ddb_flashio fio = {
.write_buf=wbuf,
.write_len=wlen,
.read_buf=rbuf,
.read_len=rlen,
.link=0,
};
return ioctl(ddb, IOCTL_DDB_FLASHIO, &fio);
}
enum {
UNKNOWN_FLASH = 0,
ATMEL_AT45DB642D = 1,
SSTI_SST25VF016B = 2,
SSTI_SST25VF032B = 3,
SSTI_SST25VF064C = 4,
SPANSION_S25FL116K = 5,
SPANSION_S25FL132K = 6,
SPANSION_S25FL164K = 7,
};
static int flashread(int ddb, uint8_t *buf, uint32_t addr, uint32_t len)
{
uint8_t cmd[4]= {0x03, (addr >> 16) & 0xff,
(addr >> 8) & 0xff, addr & 0xff};
return flashio(ddb, cmd, 4, buf, len);
}
static int flashdump(struct ddflash *ddf, uint32_t addr, uint32_t len)
{
int i, j;
uint8_t buf[32];
int bl = sizeof(buf);
for (j = 0; j < len; j += bl, addr += bl) {
flashread(ddf->fd, buf, addr, bl);
for (i = 0; i < bl; i++) {
printf("%02x ", buf[i]);
}
printf("\n");
}
}
void dump(const uint8_t *b, int l)
{
int i, j;
for (j = 0; j < l; j += 16, b += 16) {
for (i = 0; i < 16; i++)
if (i + j < l)
printf("%02x ", b[i]);
else
printf(" ");
printf(" | ");
for (i = 0; i < 16; i++)
if (i + j < l)
putchar((b[i] > 31 && b[i] < 127) ? b[i] : '.');
printf("\n");
}
}
int flashwrite_pagemode(struct ddflash *ddf, int dev, uint32_t FlashOffset,
uint8_t LockBits, uint32_t fw_off)
{
@@ -500,172 +434,6 @@ static int flash_detect(struct ddflash *ddf)
}
int FlashWriteAtmel(int dev,uint32_t FlashOffset, uint8_t *Buffer,int BufferSize)
{
int err = 0;
int BlockErase = BufferSize >= 8192;
int i;
if (BlockErase) {
for (i = 0; i < BufferSize; i += 8192 ) {
uint8_t cmd[4];
if ((i & 0xFFFF) == 0 )
printf(" Erase %08x\n",FlashOffset + i);
cmd[0] = 0x50; // Block Erase
cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
cmd[3] = 0x00;
err = flashio(dev,cmd,4,NULL,0);
if (err < 0 ) break;
while( 1 )
{
cmd[0] = 0xD7; // Read Status register
err = flashio(dev,cmd,1,&cmd[0],1);
if (err < 0 ) break;
if ((cmd[0] & 0x80) == 0x80 ) break;
}
}
}
for (i = 0; i < BufferSize; i += 1024) {
uint8_t cmd[4 + 1024];
if ((i & 0xFFFF) == 0 )
{
printf(" Program %08x\n",FlashOffset + i);
}
cmd[0] = 0x84; // Buffer 1
cmd[1] = 0x00;
cmd[2] = 0x00;
cmd[3] = 0x00;
memcpy(&cmd[4],&Buffer[i],1024);
err = flashio(dev,cmd,4 + 1024,NULL,0);
if (err < 0 ) break;
cmd[0] = BlockErase ? 0x88 : 0x83; // Buffer to Main Memory (with Erase)
cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
cmd[3] = 0x00;
err = flashio(dev,cmd,4,NULL,0);
if (err < 0 ) break;
while( 1 )
{
cmd[0] = 0xD7; // Read Status register
err = flashio(dev,cmd,1,&cmd[0],1);
if (err < 0 ) break;
if ((cmd[0] & 0x80) == 0x80 ) break;
}
if (err < 0 ) break;
}
return err;
}
int FlashWriteSSTI(int dev, uint32_t FlashOffset, uint8_t *Buffer, int BufferSize)
{
int err = 0;
uint8_t cmd[6];
int i, j;
// Must be multiple of sector size
if ((BufferSize % 4096) != 0 )
return -1;
do {
cmd[0] = 0x50; // EWSR
err = flashio(dev,cmd,1,NULL,0);
if (err < 0 )
break;
cmd[0] = 0x01; // WRSR
cmd[1] = 0x00; // BPx = 0, Unlock all blocks
err = flashio(dev,cmd,2,NULL,0);
if (err < 0 )
break;
for (i = 0; i < BufferSize; i += 4096 ) {
if ((i & 0xFFFF) == 0 )
printf(" Erase %08x\n",FlashOffset + i);
cmd[0] = 0x06; // WREN
err = flashio(dev,cmd,1,NULL,0);
if (err < 0 )
break;
cmd[0] = 0x20; // Sector erase ( 4Kb)
cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
cmd[3] = 0x00;
err = flashio(dev,cmd,4,NULL,0);
if (err < 0 )
break;
while(1) {
cmd[0] = 0x05; // RDRS
err = flashio(dev,cmd,1,&cmd[0],1);
if (err < 0 ) break;
if ((cmd[0] & 0x01) == 0 ) break;
}
if (err < 0 ) break;
}
if (err < 0 )
break;
for (j = BufferSize - 4096; j >= 0; j -= 4096 ) {
if ((j & 0xFFFF) == 0 )
printf(" Program %08x\n",FlashOffset + j);
for (i = 0; i < 4096; i += 2 ) {
if (i == 0 ) {
cmd[0] = 0x06; // WREN
err = flashio(dev,cmd,1,NULL,0);
if (err < 0 )
break;
cmd[0] = 0xAD; // AAI
cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF );
cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF );
cmd[3] = 0x00;
cmd[4] = Buffer[j+i];
cmd[5] = Buffer[j+i+1];
err = flashio(dev,cmd,6,NULL,0);
} else {
cmd[0] = 0xAD; // AAI
cmd[1] = Buffer[j+i];
cmd[2] = Buffer[j+i+1];
err = flashio(dev,cmd,3,NULL,0);
}
if (err < 0 )
break;
while(1) {
cmd[0] = 0x05; // RDRS
err = flashio(dev,cmd,1,&cmd[0],1);
if (err < 0 ) break;
if ((cmd[0] & 0x01) == 0 ) break;
}
if (err < 0 ) break;
}
if (err < 0 ) break;
cmd[0] = 0x04; // WDIS
err = flashio(dev,cmd,1,NULL,0);
if (err < 0 ) break;
}
if (err < 0 ) break;
cmd[0] = 0x50; // EWSR
err = flashio(dev,cmd,1,NULL,0);
if (err < 0 ) break;
cmd[0] = 0x01; // WRSR
cmd[1] = 0x1C; // BPx = 0, Lock all blocks
err = flashio(dev,cmd,2,NULL,0);
} while(0);
return err;
}
static int get_id(struct ddflash *ddf) {
uint8_t id[4];
@@ -677,19 +445,6 @@ static int get_id(struct ddflash *ddf) {
ddf->id.subvendor, ddf->id.subdevice,
ddf->id.hw, ddf->id.regmap);
#endif
if (ddf->id.device == 0x0011)
ddf->type = 1;
if (ddf->id.device == 0x0201)
ddf->type = 2;
if (ddf->id.device == 0x02)
ddf->type = 3;
if (ddf->id.device == 0x03)
ddf->type = 0;
if (ddf->id.device == 0x0300)
ddf->type = 4;
if (ddf->id.device == 0x0320)
ddf->type = 5;
return 0;
}

494
apps/octonet/ddtest.c
View File

@@ -1,3 +1,4 @@
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
@@ -12,8 +13,6 @@
#include "flash.h"
static uint32_t linknr = 0;
typedef int (*COMMAND_FUNCTION)(int dev, int argc, char* argv[], uint32_t Flags);
enum {
@@ -21,17 +20,6 @@ enum {
SILENT_FLAG = 0x00000002,
};
enum {
UNKNOWN_FLASH = 0,
ATMEL_AT45DB642D = 1,
SSTI_SST25VF016B = 2,
SSTI_SST25VF032B = 3,
SSTI_SST25VF064C = 4,
SPANSION_S25FL116K = 5,
SPANSION_S25FL132K = 6,
SPANSION_S25FL164K = 7,
};
struct SCommand
{
char* Name;
@@ -42,94 +30,25 @@ struct SCommand
// --------------------------------------------------------------------------------------------
void Dump(const uint8_t *b, uint32_t start, int l)
{
int i, j;
for (j = 0; j < l; j += 16, b += 16) {
printf("%08x: ", start + j);
for (i = 0; i < 16; i++)
if (i + j < l)
printf("%02x ", b[i]);
else
printf(" ");
printf(" |");
for (i = 0; i < 16; i++)
if (i + j < l)
putchar((b[i] > 31 && b[i] < 127) ? b[i] : '.');
printf("|\n");
}
}
int readreg(int dev, uint32_t RegAddress, uint32_t *pRegValue)
{
struct ddb_reg reg = { .reg = RegAddress };
int ret;
ret = ioctl(dev, IOCTL_DDB_READ_REG, &reg);
if (ret < 0)
return ret;
if (pRegValue)
*pRegValue = reg.val;
return 0;
}
int writereg(int dev, uint32_t RegAddress, uint32_t RegValue)
{
struct ddb_reg reg = { .reg = RegAddress, .val = RegValue};
return ioctl(dev, IOCTL_DDB_WRITE_REG, &reg);
}
int FlashIO(int ddb, uint8_t *wbuf, uint32_t wlen, uint8_t *rbuf, uint32_t rlen)
{
struct ddb_flashio fio = {
.write_buf=wbuf,
.write_len=wlen,
.read_buf=rbuf,
.read_len=rlen,
.link=linknr,
};
return ioctl(ddb, IOCTL_DDB_FLASHIO, &fio);
}
int flashread(int ddb, uint8_t *buf, uint32_t addr, uint32_t len)
{
int ret;
uint8_t cmd[4];
uint32_t l;
while (len) {
cmd[0] = 3;
cmd[1] = (addr >> 16) & 0xff;
cmd[2] = (addr >> 8) & 0xff;
cmd[3] = addr & 0xff;
if (len > 1024)
l = 1024;
else
l = len;
ret = FlashIO(ddb, cmd, 4, buf, l);
if (ret < 0)
return ret;
addr += l;
buf += l;
len -= l;
}
return 0;
}
int ReadFlash(int ddb, int argc, char *argv[], uint32_t Flags)
{
uint32_t Start;
uint32_t Len;
uint8_t *Buffer;
int fd;
if (argc < 2 )
return -1;
Start = strtoul(argv[0],NULL,16);
Len = strtoul(argv[1],NULL,16);
if (argc == 3) {
fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC);
if (fd < 0) {
printf("Could not open file %s\n", argv[2]);
return -1;
}
}
Buffer = malloc(Len);
if (flashread(ddb, Buffer, Start, Len) < 0) {
@@ -138,68 +57,43 @@ int ReadFlash(int ddb, int argc, char *argv[], uint32_t Flags)
return 0;
}
Dump(Buffer,Start,Len);
if (argc == 3) {
write(fd, Buffer, Len);
close(fd);
} else
Dump(Buffer,Start,Len);
free(Buffer);
return 0;
}
int FlashDetect(int dev)
int ReadSave(int ddb, int argc, char *argv[], uint32_t Flags)
{
uint8_t Cmd = 0x9F;
uint8_t Id[3];
int r = FlashIO(dev, &Cmd, 1, Id, 3);
if (r < 0)
return r;
if (Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x41)
r = SSTI_SST25VF016B;
else if (Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x4A)
r = SSTI_SST25VF032B;
else if ( Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x4B )
r = SSTI_SST25VF064C;
else if ( Id[0] == 0x01 && Id[1] == 0x40 && Id[2] == 0x15 )
r = SPANSION_S25FL116K;
else if ( Id[0] == 0x01 && Id[1] == 0x40 && Id[2] == 0x16 )
r = SPANSION_S25FL132K;
else if ( Id[0] == 0x01 && Id[1] == 0x40 && Id[2] == 0x17 )
r = SPANSION_S25FL164K;
else if ( Id[0] == 0x1F && Id[1] == 0x28)
r = ATMEL_AT45DB642D;
else
r = UNKNOWN_FLASH;
switch(r) {
case UNKNOWN_FLASH :
printf("Unknown Flash Flash ID = %02x %02x %02x\n",Id[0],Id[1],Id[2]);
break;
case ATMEL_AT45DB642D :
printf("Flash: Atmel AT45DB642D 64 MBit\n");
break;
case SSTI_SST25VF016B :
printf("Flash: SSTI SST25VF016B 16 MBit\n");
break;
case SSTI_SST25VF032B :
printf("Flash: SSTI SST25VF032B 32 MBit\n");
break;
case SSTI_SST25VF064C :
printf("Flash: SSTI SST25VF064C 64 MBit\n");
break;
case SPANSION_S25FL116K :
printf("Flash: SPANSION S25FL116K 16 MBit\n");
break;
case SPANSION_S25FL132K :
printf("Flash: SPANSION S25FL132K 32 MBit\n");
break;
case SPANSION_S25FL164K :
printf("Flash: SPANSION S25FL164K 64 MBit\n");
break;
uint32_t Start;
uint32_t Len;
uint8_t *Buffer;
int fd;
if (argc < 3 )
return -1;
Start = strtoul(argv[0],NULL,16);
Len = strtoul(argv[1],NULL,16);
Buffer = malloc(Len);
if (flashread(ddb, Buffer, Start, Len) < 0) {
printf("flashread error\n");
free(Buffer);
return 0;
}
return r;
free(Buffer);
return 0;
}
int FlashChipEraseAtmel(int dev)
{
int err = 0;
@@ -214,12 +108,12 @@ int FlashChipEraseAtmel(int dev)
Cmd[1] = ( (( i ) >> 16) & 0xFF );
Cmd[2] = ( (( i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = FlashIO(dev,Cmd,4,NULL,0);
err = flashio(dev,Cmd,4,NULL,0);
if( err < 0 )
break;
while (1) {
Cmd[0] = 0xD7; // Read Status register
err = FlashIO(dev,Cmd,1,&Cmd[0],1);
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x80) == 0x80 ) break;
}
@@ -237,25 +131,25 @@ int FlashChipEraseSSTI(int dev)
do {
Cmd[0] = 0x50; // EWSR
err = FlashIO(dev,Cmd,1,NULL,0);
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x00; // BPx = 0, Unlock all blocks
err = FlashIO(dev,Cmd,2,NULL,0);
err = flashio(dev,Cmd,2,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x06; // WREN
err = FlashIO(dev,Cmd,1,NULL,0);
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x60; // CHIP Erase
err = FlashIO(dev,Cmd,1,NULL,0);
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
while(1) {
Cmd[0] = 0x05; // RDRS
err = FlashIO(dev,Cmd,1,&Cmd[0],1);
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
@@ -263,12 +157,12 @@ int FlashChipEraseSSTI(int dev)
break;
Cmd[0] = 0x50; // EWSR
err = FlashIO(dev,Cmd,1,NULL,0);
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x1C; // BPx = 0, Lock all blocks
err = FlashIO(dev,Cmd,2,NULL,0);
err = flashio(dev,Cmd,2,NULL,0);
}
while(0);
@@ -278,286 +172,6 @@ int FlashChipEraseSSTI(int dev)
}
int FlashWriteAtmel(int dev,uint32_t FlashOffset,uint8_t * Buffer,int BufferSize)
{
int err = 0, i;
int BlockErase = BufferSize >= 8192;
uint8_t Cmd[4];
if( BlockErase ) {
for(i = 0; i < BufferSize; i += 8192 ) {
if( (i & 0xFFFF) == 0 )
{
printf(" Erase %08x\n",FlashOffset + i);
}
Cmd[0] = 0x50; // Block Erase
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = FlashIO(dev,Cmd,4,NULL,0);
if( err < 0 ) break;
while(1) {
Cmd[0] = 0xD7; // Read Status register
err = FlashIO(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x80) == 0x80 ) break;
}
}
}
for(i = 0; i < BufferSize; i += 1024 )
{
if( (i & 0xFFFF) == 0 )
{
printf(" Programm %08x\n",FlashOffset + i);
}
uint8_t Cmd[4 + 1024];
Cmd[0] = 0x84; // Buffer 1
Cmd[1] = 0x00;
Cmd[2] = 0x00;
Cmd[3] = 0x00;
memcpy(&Cmd[4],&Buffer[i],1024);
err = FlashIO(dev,Cmd,4 + 1024,NULL,0);
if( err < 0 ) break;
Cmd[0] = BlockErase ? 0x88 : 0x83; // Buffer to Main Memory (with Erase)
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = FlashIO(dev,Cmd,4,NULL,0);
if( err < 0 ) break;
while(1)
{
Cmd[0] = 0xD7; // Read Status register
err = FlashIO(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x80) == 0x80 ) break;
}
if( err < 0 ) break;
}
return err;
}
// **************************************************************************************
// BUG: Erasing and writing an incomplete image will result in an failure to boot golden image.
// FIX: Write the new image from high to low addresses
int FlashWriteSSTI(int dev,uint32_t FlashOffset,uint8_t * Buffer,int BufferSize)
{
int err = 0, i, j;
uint8_t Cmd[6];
if( (BufferSize % 4096) != 0 ) return -1; // Must be multiple of sector size
do
{
Cmd[0] = 0x50; // EWSR
err = FlashIO(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x00; // BPx = 0, Unlock all blocks
err = FlashIO(dev,Cmd,2,NULL,0);
if( err < 0 ) break;
for (i = 0; i < BufferSize; i += 4096 )
{
if( (i & 0xFFFF) == 0 )
{
printf(" Erase %08x\n",FlashOffset + i);
}
Cmd[0] = 0x06; // WREN
err = FlashIO(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x20; // Sector erase ( 4Kb)
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = FlashIO(dev,Cmd,4,NULL,0);
if( err < 0 ) break;
while(1)
{
Cmd[0] = 0x05; // RDRS
err = FlashIO(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 ) break;
for (j = BufferSize - 4096; j >= 0; j -= 4096 )
{
if( (j & 0xFFFF) == 0 )
{
printf(" Programm %08x\n",FlashOffset + j);
}
for (i = 0; i < 4096; i += 2 )
{
if( i == 0 )
{
Cmd[0] = 0x06; // WREN
err = FlashIO(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0xAD; // AAI
Cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF );
Cmd[3] = 0x00;
Cmd[4] = Buffer[j+i];
Cmd[5] = Buffer[j+i+1];
err = FlashIO(dev,Cmd,6,NULL,0);
}
else
{
Cmd[0] = 0xAD; // AAI
Cmd[1] = Buffer[j+i];
Cmd[2] = Buffer[j+i+1];
err = FlashIO(dev,Cmd,3,NULL,0);
}
if( err < 0 ) break;
while(1)
{
Cmd[0] = 0x05; // RDRS
err = FlashIO(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 ) break;
Cmd[0] = 0x04; // WDIS
err = FlashIO(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
}
if( err < 0 ) break;
Cmd[0] = 0x50; // EWSR
err = FlashIO(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x1C; // BPx = 0, Lock all blocks
err = FlashIO(dev,Cmd,2,NULL,0);
}
while(0);
return err;
}
int FlashWritePageMode(int dev, uint32_t FlashOffset,
uint8_t *Buffer,int BufferSize,uint8_t LockBits)
{
int err = 0;
uint8_t Cmd[260];
int i, j;
if( (BufferSize % 4096) != 0 ) return -1; // Must be multiple of sector size
do
{
Cmd[0] = 0x50; // EWSR
err = FlashIO(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x00; // BPx = 0, Unlock all blocks
err = FlashIO(dev,Cmd,2,NULL,0);
if( err < 0 ) break;
for(i = 0; i < BufferSize; i += 4096 )
{
if( (i & 0xFFFF) == 0 )
{
printf(" Erase %08x\n",FlashOffset + i);
}
Cmd[0] = 0x06; // WREN
err = FlashIO(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x20; // Sector erase ( 4Kb)
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = FlashIO(dev,Cmd,4,NULL,0);
if( err < 0 ) break;
while(1)
{
Cmd[0] = 0x05; // RDRS
err = FlashIO(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 ) break;
for(j = BufferSize - 256; j >= 0; j -= 256 )
{
if( (j & 0xFFFF) == 0 )
{
printf(" Programm %08x\n",FlashOffset + j);
}
Cmd[0] = 0x06; // WREN
err = FlashIO(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x02; // PP
Cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF );
Cmd[3] = 0x00;
memcpy(&Cmd[4],&Buffer[j],256);
err = FlashIO(dev,Cmd,260,NULL,0);
if( err < 0 ) break;
while(1)
{
Cmd[0] = 0x05; // RDRS
err = FlashIO(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 ) break;
Cmd[0] = 0x50; // EWSR
err = FlashIO(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = LockBits; // BPx = 0, Lock all blocks
err = FlashIO(dev,Cmd,2,NULL,0);
}
while(0);
return err;
}
// --------------------------------------------------------------------------------------------
int ReadDeviceMemory(int dev,int argc, char* argv[],uint32_t Flags)
{
@@ -693,7 +307,7 @@ int GetSetRegister(int dev,int argc, char* argv[],uint32_t Flags)
// -----------------------------------------------------------------------------------------------------------
// -----------------------------------------------------------------------------------------------------------
int FlashIOC(int dev,int argc, char* argv[],uint32_t Flags)
int flashioc(int dev,int argc, char* argv[],uint32_t Flags)
{
uint8_t *Buffer;
uint32_t tmp = 0, i;
@@ -718,7 +332,7 @@ int FlashIOC(int dev,int argc, char* argv[],uint32_t Flags)
Buffer[i] = (uint8_t) tmp;
}
if( FlashIO(dev,Buffer,WriteLen,Buffer,ReadLen) < 0 )
if( flashio(dev,Buffer,WriteLen,Buffer,ReadLen) < 0 )
{
return 0;
}
@@ -1655,7 +1269,7 @@ static int read_sfpd(int dev, uint8_t adr, uint8_t *val)
uint8_t cmd[5] = { 0x5a, 0, 0, adr, 00 };
int r;
r = FlashIO(dev, cmd, 5, val, 1);
r = flashio(dev, cmd, 5, val, 1);
if (r < 0)
return r;
return 0;
@@ -1667,7 +1281,7 @@ static int read_sst_id(int dev, uint8_t *id)
uint8_t buf[9];
int r;
r = FlashIO(dev, cmd, 2, buf, 9);
r = flashio(dev, cmd, 2, buf, 9);
if (r < 0)
return r;
memcpy(id, buf + 1, 8);
@@ -1696,10 +1310,10 @@ int read_id(int dev, int argc, char* argv[], uint32_t Flags)
break;
default:
printf("Unsupported Flash\n");
break;
return -1;
}
printf("ID: ");
for (i = 0; i < 8; i++)
for (i = 0; i < len; i++)
printf("%02x ", Id[i]);
printf("\n");
@@ -1712,13 +1326,13 @@ struct SCommand CommandTable[] =
{ "memwrite", WriteDeviceMemory, 1, "Write Device Memory : memwrite <start> <values(8)> .." },
{ "register", GetSetRegister, 1, "Get/Set Register : reg <regname>|<[0x]regnum> [[0x]value(32)]" },
{ "flashread", ReadFlash, 1, "Read Flash : flashread <start> <count>" },
{ "flashio", FlashIOC, 1, "Flash IO : flashio <write data>.. <read count>" },
{ "flashread", ReadFlash, 1, "Read Flash : flashread <start> <count> [<Filename>]" },
{ "flashio", flashioc, 1, "Flash IO : flashio <write data>.. <read count>" },
{ "flashprog", FlashProg, 1, "Flash Programming : flashprog <FileName> [<address>]" },
{ "flashprog", FlashProg, 1, "Flash Programming : flashprog -SubVendorID <id>" },
{ "flashprog", FlashProg, 1, "Flash Programming : flashprog -Jump <address>" },
{ "flashverify", FlashVerify, 1, "Flash Verify : flashverify <FileName> [<address>]" },
{ "flasherase", FlashErase, 1, "FlashErase : flasherase" },
//{ "flasherase", FlashErase, 1, "FlashErase : flasherase" },
//{ "flashtest", FlashTest, 1, "FlashTest : flashtest" },

614
apps/octonet/flash.c Normal file
View File

@@ -0,0 +1,614 @@
enum {
UNKNOWN_FLASH = 0,
ATMEL_AT45DB642D = 1,
SSTI_SST25VF016B = 2,
SSTI_SST25VF032B = 3,
SSTI_SST25VF064C = 4,
SPANSION_S25FL116K = 5,
SPANSION_S25FL132K = 6,
SPANSION_S25FL164K = 7,
};
static uint32_t linknr = 0;
int flashio(int ddb, uint8_t *wbuf, uint32_t wlen, uint8_t *rbuf, uint32_t rlen)
{
struct ddb_flashio fio = {
.write_buf=wbuf,
.write_len=wlen,
.read_buf=rbuf,
.read_len=rlen,
.link=linknr,
};
return ioctl(ddb, IOCTL_DDB_FLASHIO, &fio);
}
int FlashDetect(int dev)
{
uint8_t Cmd = 0x9F;
uint8_t Id[3];
int r = flashio(dev, &Cmd, 1, Id, 3);
if (r < 0)
return r;
if (Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x41)
r = SSTI_SST25VF016B;
else if (Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x4A)
r = SSTI_SST25VF032B;
else if ( Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x4B )
r = SSTI_SST25VF064C;
else if ( Id[0] == 0x01 && Id[1] == 0x40 && Id[2] == 0x15 )
r = SPANSION_S25FL116K;
else if ( Id[0] == 0x01 && Id[1] == 0x40 && Id[2] == 0x16 )
r = SPANSION_S25FL132K;
else if ( Id[0] == 0x01 && Id[1] == 0x40 && Id[2] == 0x17 )
r = SPANSION_S25FL164K;
else if ( Id[0] == 0x1F && Id[1] == 0x28)
r = ATMEL_AT45DB642D;
else
r = UNKNOWN_FLASH;
switch(r) {
case UNKNOWN_FLASH :
printf("Unknown Flash Flash ID = %02x %02x %02x\n",Id[0],Id[1],Id[2]);
break;
case ATMEL_AT45DB642D :
printf("Flash: Atmel AT45DB642D 64 MBit\n");
break;
case SSTI_SST25VF016B :
printf("Flash: SSTI SST25VF016B 16 MBit\n");
break;
case SSTI_SST25VF032B :
printf("Flash: SSTI SST25VF032B 32 MBit\n");
break;
case SSTI_SST25VF064C :
printf("Flash: SSTI SST25VF064C 64 MBit\n");
break;
case SPANSION_S25FL116K :
printf("Flash: SPANSION S25FL116K 16 MBit\n");
break;
case SPANSION_S25FL132K :
printf("Flash: SPANSION S25FL132K 32 MBit\n");
break;
case SPANSION_S25FL164K :
printf("Flash: SPANSION S25FL164K 64 MBit\n");
break;
}
return r;
}
static int flashdetect(int fd, uint32_t *sector_size, uint32_t *flash_size)
{
uint8_t cmd = 0x9F;
uint8_t id[3];
int flash_type;
int r = flashio(fd, &cmd, 1, id, 3);
if (r < 0)
return r;
if (id[0] == 0xBF && id[1] == 0x25 && id[2] == 0x41) {
flash_type = SSTI_SST25VF016B;
printf("Flash: SSTI SST25VF016B 16 MBit\n");
*sector_size = 4096;
*flash_size = 0x200000;
} else if (id[0] == 0xBF && id[1] == 0x25 && id[2] == 0x4A) {
flash_type = SSTI_SST25VF032B;
printf("Flash: SSTI SST25VF032B 32 MBit\n");
*sector_size = 4096;
*flash_size = 0x400000;
} else if (id[0] == 0xBF && id[1] == 0x25 && id[2] == 0x4B) {
flash_type = SSTI_SST25VF064C;
printf("Flash: SSTI SST25VF064C 64 MBit\n");
*sector_size = 4096;
*flash_size = 0x800000;
} else if (id[0] == 0x01 && id[1] == 0x40 && id[2] == 0x15) {
flash_type = SPANSION_S25FL116K;
printf("Flash: SPANSION S25FL116K 16 MBit\n");
*sector_size = 4096;
*flash_size = 0x200000;
} else if (id[0] == 0x01 && id[1] == 0x40 && id[2] == 0x16) {
flash_type = SPANSION_S25FL132K;
printf("Flash: SPANSION S25FL132K 32 MBit\n");
*sector_size = 4096;
*flash_size = 0x400000;
} else if (id[0] == 0x01 && id[1] == 0x40 && id[2] == 0x17) {
flash_type = SPANSION_S25FL164K;
printf("Flash: SPANSION S25FL164K 64 MBit\n");
*sector_size = 4096;
*flash_size = 0x800000;
} else if (id[0] == 0x1F && id[1] == 0x28) {
flash_type = ATMEL_AT45DB642D;
printf("Flash: Atmel AT45DB642D 64 MBit\n");
*sector_size = 1024;
*flash_size = 0x800000;
} else {
printf("Unknown Flash Flash ID = %02x %02x %02x\n", id[0], id[1], id[2]);
return -1;
}
return flash_type;
}
#if 1
int flashread(int ddb, uint8_t *buf, uint32_t addr, uint32_t len)
{
int ret;
uint8_t cmd[4];
uint32_t l;
while (len) {
cmd[0] = 3;
cmd[1] = (addr >> 16) & 0xff;
cmd[2] = (addr >> 8) & 0xff;
cmd[3] = addr & 0xff;
if (len > 1024)
l = 1024;
else
l = len;
ret = flashio(ddb, cmd, 4, buf, l);
if (ret < 0)
return ret;
addr += l;
buf += l;
len -= l;
}
return 0;
}
#else
static int flashread(int ddb, uint8_t *buf, uint32_t addr, uint32_t len)
{
uint8_t cmd[4]= {0x03, (addr >> 16) & 0xff,
(addr >> 8) & 0xff, addr & 0xff};
return flashio(ddb, cmd, 4, buf, len);
}
#endif
int flashdump(int ddb, uint32_t addr, uint32_t len)
{
int i, j;
uint8_t buf[32];
int bl = sizeof(buf);
for (j=0; j<len; j+=bl, addr+=bl) {
flashread(ddb, buf, addr, bl);
for (i=0; i<bl; i++) {
printf("%02x ", buf[i]);
}
printf("\n");
}
}
int readreg(int dev, uint32_t RegAddress, uint32_t *pRegValue)
{
struct ddb_reg reg = { .reg = RegAddress };
int ret;
ret = ioctl(dev, IOCTL_DDB_READ_REG, &reg);
if (ret < 0)
return ret;
if (pRegValue)
*pRegValue = reg.val;
return 0;
}
int writereg(int dev, uint32_t RegAddress, uint32_t RegValue)
{
struct ddb_reg reg = { .reg = RegAddress, .val = RegValue};
return ioctl(dev, IOCTL_DDB_WRITE_REG, &reg);
}
void dump(const uint8_t *b, int l)
{
int i, j;
for (j = 0; j < l; j += 16, b += 16) {
for (i = 0; i < 16; i++)
if (i + j < l)
printf("%02x ", b[i]);
else
printf(" ");
printf(" | ");
for (i = 0; i < 16; i++)
if (i + j < l)
putchar((b[i] > 31 && b[i] < 127) ? b[i] : '.');
printf("\n");
}
}
void Dump(const uint8_t *b, uint32_t start, int l)
{
int i, j;
for (j = 0; j < l; j += 16, b += 16) {
printf("%08x: ", start + j);
for (i = 0; i < 16; i++)
if (i + j < l)
printf("%02x ", b[i]);
else
printf(" ");
printf(" |");
for (i = 0; i < 16; i++)
if (i + j < l)
putchar((b[i] > 31 && b[i] < 127) ? b[i] : '.');
printf("|\n");
}
}
int FlashWriteAtmel(int dev,uint32_t FlashOffset, uint8_t *Buffer,int BufferSize)
{
int err = 0;
int BlockErase = BufferSize >= 8192;
int i;
if (BlockErase) {
for(i = 0; i < BufferSize; i += 8192 ) {
uint8_t Cmd[4];
if( (i & 0xFFFF) == 0 )
printf(" Erase %08x\n",FlashOffset + i);
Cmd[0] = 0x50; // Block Erase
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = flashio(dev,Cmd,4,NULL,0);
if( err < 0 ) break;
while( 1 )
{
Cmd[0] = 0xD7; // Read Status register
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x80) == 0x80 ) break;
}
}
}
for(i = 0; i < BufferSize; i += 1024 )
{
uint8_t Cmd[4 + 1024];
if( (i & 0xFFFF) == 0 )
{
printf(" Program %08x\n",FlashOffset + i);
}
Cmd[0] = 0x84; // Buffer 1
Cmd[1] = 0x00;
Cmd[2] = 0x00;
Cmd[3] = 0x00;
memcpy(&Cmd[4],&Buffer[i],1024);
err = flashio(dev,Cmd,4 + 1024,NULL,0);
if( err < 0 ) break;
Cmd[0] = BlockErase ? 0x88 : 0x83; // Buffer to Main Memory (with Erase)
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = flashio(dev,Cmd,4,NULL,0);
if( err < 0 ) break;
while( 1 )
{
Cmd[0] = 0xD7; // Read Status register
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x80) == 0x80 ) break;
}
if( err < 0 ) break;
}
return err;
}
int FlashWriteSSTI(int dev, uint32_t FlashOffset, uint8_t *Buffer, int BufferSize)
{
int err = 0;
uint8_t cmd[6];
int i, j;
// Must be multiple of sector size
if ((BufferSize % 4096) != 0 )
return -1;
do {
cmd[0] = 0x50; // EWSR
err = flashio(dev,cmd,1,NULL,0);
if (err < 0 )
break;
cmd[0] = 0x01; // WRSR
cmd[1] = 0x00; // BPx = 0, Unlock all blocks
err = flashio(dev,cmd,2,NULL,0);
if (err < 0 )
break;
for (i = 0; i < BufferSize; i += 4096 ) {
if ((i & 0xFFFF) == 0 )
printf(" Erase %08x\n",FlashOffset + i);
cmd[0] = 0x06; // WREN
err = flashio(dev,cmd,1,NULL,0);
if (err < 0 )
break;
cmd[0] = 0x20; // Sector erase ( 4Kb)
cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
cmd[3] = 0x00;
err = flashio(dev,cmd,4,NULL,0);
if (err < 0 )
break;
while(1) {
cmd[0] = 0x05; // RDRS
err = flashio(dev,cmd,1,&cmd[0],1);
if (err < 0 ) break;
if ((cmd[0] & 0x01) == 0 ) break;
}
if (err < 0 ) break;
}
if (err < 0 )
break;
for (j = BufferSize - 4096; j >= 0; j -= 4096 ) {
if ((j & 0xFFFF) == 0 )
printf(" Program %08x\n",FlashOffset + j);
for (i = 0; i < 4096; i += 2 ) {
if (i == 0 ) {
cmd[0] = 0x06; // WREN
err = flashio(dev,cmd,1,NULL,0);
if (err < 0 )
break;
cmd[0] = 0xAD; // AAI
cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF );
cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF );
cmd[3] = 0x00;
cmd[4] = Buffer[j+i];
cmd[5] = Buffer[j+i+1];
err = flashio(dev,cmd,6,NULL,0);
} else {
cmd[0] = 0xAD; // AAI
cmd[1] = Buffer[j+i];
cmd[2] = Buffer[j+i+1];
err = flashio(dev,cmd,3,NULL,0);
}
if (err < 0 )
break;
while(1) {
cmd[0] = 0x05; // RDRS
err = flashio(dev,cmd,1,&cmd[0],1);
if (err < 0 ) break;
if ((cmd[0] & 0x01) == 0 ) break;
}
if (err < 0 ) break;
}
if (err < 0 ) break;
cmd[0] = 0x04; // WDIS
err = flashio(dev,cmd,1,NULL,0);
if (err < 0 ) break;
}
if (err < 0 ) break;
cmd[0] = 0x50; // EWSR
err = flashio(dev,cmd,1,NULL,0);
if (err < 0 ) break;
cmd[0] = 0x01; // WRSR
cmd[1] = 0x1C; // BPx = 0, Lock all blocks
err = flashio(dev,cmd,2,NULL,0);
} while(0);
return err;
}
int FlashWriteSSTI_B(int dev, uint32_t FlashOffset, uint8_t *Buffer, int BufferSize)
{
int err = 0;
uint8_t Cmd[6];
int i, j;
// Must be multiple of sector size
if( (BufferSize % 4096) != 0 )
return -1;
do {
Cmd[0] = 0x50; // EWSR
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 )
break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x00; // BPx = 0, Unlock all blocks
err = flashio(dev,Cmd,2,NULL,0);
if( err < 0 )
break;
for(i = 0; i < BufferSize; i += 4096 ) {
if( (i & 0xFFFF) == 0 )
printf(" Erase %08x\n",FlashOffset + i);
Cmd[0] = 0x06; // WREN
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 )
break;
Cmd[0] = 0x20; // Sector erase ( 4Kb)
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = flashio(dev,Cmd,4,NULL,0);
if( err < 0 )
break;
while(1) {
Cmd[0] = 0x05; // RDRS
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 )
break;
for(j = BufferSize - 4096; j >= 0; j -= 4096 ) {
if( (j & 0xFFFF) == 0 )
printf(" Program %08x\n",FlashOffset + j);
for(i = 0; i < 4096; i += 2 ) {
if( i == 0 ) {
Cmd[0] = 0x06; // WREN
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 )
break;
Cmd[0] = 0xAD; // AAI
Cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF );
Cmd[3] = 0x00;
Cmd[4] = Buffer[j+i];
Cmd[5] = Buffer[j+i+1];
err = flashio(dev,Cmd,6,NULL,0);
} else {
Cmd[0] = 0xAD; // AAI
Cmd[1] = Buffer[j+i];
Cmd[2] = Buffer[j+i+1];
err = flashio(dev,Cmd,3,NULL,0);
}
if( err < 0 )
break;
while(1) {
Cmd[0] = 0x05; // RDRS
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 ) break;
Cmd[0] = 0x04; // WDIS
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
}
if( err < 0 ) break;
Cmd[0] = 0x50; // EWSR
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x1C; // BPx = 0, Lock all blocks
err = flashio(dev,Cmd,2,NULL,0);
} while(0);
return err;
}
int FlashWritePageMode(int dev, uint32_t FlashOffset,
uint8_t *Buffer,int BufferSize,uint8_t LockBits)
{
int err = 0;
uint8_t Cmd[260];
int i, j;
if( (BufferSize % 4096) != 0 ) return -1; // Must be multiple of sector size
do
{
Cmd[0] = 0x50; // EWSR
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = 0x00; // BPx = 0, Unlock all blocks
err = flashio(dev,Cmd,2,NULL,0);
if( err < 0 ) break;
for(i = 0; i < BufferSize; i += 4096 )
{
if( (i & 0xFFFF) == 0 )
{
printf(" Erase %08x\n",FlashOffset + i);
}
Cmd[0] = 0x06; // WREN
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x20; // Sector erase ( 4Kb)
Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF );
Cmd[3] = 0x00;
err = flashio(dev,Cmd,4,NULL,0);
if( err < 0 ) break;
while(1)
{
Cmd[0] = 0x05; // RDRS
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 ) break;
for(j = BufferSize - 256; j >= 0; j -= 256 )
{
if( (j & 0xFFFF) == 0 )
{
printf(" Programm %08x\n",FlashOffset + j);
}
Cmd[0] = 0x06; // WREN
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x02; // PP
Cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF );
Cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF );
Cmd[3] = 0x00;
memcpy(&Cmd[4],&Buffer[j],256);
err = flashio(dev,Cmd,260,NULL,0);
if( err < 0 ) break;
while(1)
{
Cmd[0] = 0x05; // RDRS
err = flashio(dev,Cmd,1,&Cmd[0],1);
if( err < 0 ) break;
if( (Cmd[0] & 0x01) == 0 ) break;
}
if( err < 0 ) break;
}
if( err < 0 ) break;
Cmd[0] = 0x50; // EWSR
err = flashio(dev,Cmd,1,NULL,0);
if( err < 0 ) break;
Cmd[0] = 0x01; // WRSR
Cmd[1] = LockBits; // BPx = 0, Lock all blocks
err = flashio(dev,Cmd,2,NULL,0);
}
while(0);
return err;
}

2
apps/octonet/flash.h
View File

@@ -61,3 +61,5 @@ struct ddb_i2c_msg {
#define IOCTL_DDB_WRITE_MDIO _IOR(DDB_MAGIC, 0x09, struct ddb_mdio)
#define IOCTL_DDB_READ_I2C _IOWR(DDB_MAGIC, 0x0a, struct ddb_i2c_msg)
#define IOCTL_DDB_WRITE_I2C _IOR(DDB_MAGIC, 0x0b, struct ddb_i2c_msg)
#include "flash.c"

47
apps/setmod2.c Normal file
View File

@@ -0,0 +1,47 @@
#include <errno.h>
#include <stdio.h>
#include <ctype.h>
#include <string.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <stdint.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <pthread.h>
#include <linux/dvb/mod.h>
static int set_property(int fd, uint32_t cmd, uint32_t data)
{
struct dtv_property p;
struct dtv_properties c;
int ret;
p.cmd = cmd;
c.num = 1;
c.props = &p;
p.u.data = data;
ret = ioctl(fd, FE_SET_PROPERTY, &c);
if (ret < 0) {
fprintf(stderr, "FE_SET_PROPERTY returned %d\n", errno);
return -1;
}
return 0;
}
int main()
{
int fd;
struct dvb_mod_params mp;
struct dvb_mod_channel_params mc;
fd = open("/dev/dvb/adapter0/mod0", O_RDONLY);
set_property(fd, MODULATOR_MODULATION, QAM_256);
set_property(fd, MODULATOR_SYMBOL_RATE, 6900000);
set_property(fd, MODULATOR_FREQUENCY, 114000000);
close(fd);
}

445
ddbridge/ddbridge-core.c
View File

@@ -26,7 +26,7 @@
DEFINE_MUTEX(redirect_lock);
static int ci_bitrate = 72000;
static int ci_bitrate = 70000;
module_param(ci_bitrate, int, 0444);
MODULE_PARM_DESC(ci_bitrate, " Bitrate in KHz for output to CI.");
@@ -66,6 +66,10 @@ static int no_init;
module_param(no_init, int, 0444);
MODULE_PARM_DESC(no_init, "do not initialize most devices");
static int stv0910_single;
module_param(stv0910_single, int, 0444);
MODULE_PARM_DESC(no_init, "use stv0910 cards as single demods");
#define DDB_MAX_ADAPTER 64
static struct ddb *ddbs[DDB_MAX_ADAPTER];
@@ -285,7 +289,6 @@ static struct ddb_regmap octopus_mod_map = {
.channel = &octopus_mod_channel,
};
static struct ddb_regmap octopus_mod_2_map = {
.irq_version = 2,
.irq_base_odma = 64,
@@ -306,17 +309,67 @@ static struct ddb_info ddb_s2_48 = {
.port_num = 4,
.i2c_mask = 0x01,
.board_control = 1,
.tempmon_irq = 24,
};
static struct ddb_info ddb_ct_8 = {
static struct ddb_info ddb_ct2_8 = {
.type = DDB_OCTOPUS_MAX_CT,
.name = "Digital Devices MAX CT8",
.name = "Digital Devices MAX A8 CT2",
.regmap = &octopus_map,
.port_num = 4,
.i2c_mask = 0x0f,
.board_control = 0x0ff,
.board_control_2 = 0xf00,
.ts_quirks = TS_QUIRK_SERIAL,
.tempmon_irq = 24,
};
static struct ddb_info ddb_c2t2_8 = {
.type = DDB_OCTOPUS_MAX_CT,
.name = "Digital Devices MAX A8 C2T2",
.regmap = &octopus_map,
.port_num = 4,
.i2c_mask = 0x0f,
.board_control = 0x0ff,
.board_control_2 = 0xf00,
.ts_quirks = TS_QUIRK_SERIAL,
.tempmon_irq = 24,
};
static struct ddb_info ddb_isdbt_8 = {
.type = DDB_OCTOPUS_MAX_CT,
.name = "Digital Devices MAX A8 ISDBT",
.regmap = &octopus_map,
.port_num = 4,
.i2c_mask = 0x0f,
.board_control = 0x0ff,
.board_control_2 = 0xf00,
.ts_quirks = TS_QUIRK_SERIAL,
.tempmon_irq = 24,
};
static struct ddb_info ddb_c2t2i_v0_8 = {
.type = DDB_OCTOPUS_MAX_CT,
.name = "Digital Devices MAX A8 C2T2I V0",
.regmap = &octopus_map,
.port_num = 4,
.i2c_mask = 0x0f,
.board_control = 0x0ff,
.board_control_2 = 0xf00,
.ts_quirks = TS_QUIRK_SERIAL | TS_QUIRK_ALT_OSC,
.tempmon_irq = 24,
};
static struct ddb_info ddb_c2t2i_8 = {
.type = DDB_OCTOPUS_MAX_CT,
.name = "Digital Devices MAX A8 C2T2I",
.regmap = &octopus_map,
.port_num = 4,
.i2c_mask = 0x0f,
.board_control = 0x0ff,
.board_control_2 = 0xf00,
.ts_quirks = TS_QUIRK_SERIAL,
.tempmon_irq = 24,
};
@@ -383,7 +436,7 @@ static int ddb_unredirect(struct ddb_port *port)
struct ddb_input *oredi, *iredi = 0;
struct ddb_output *iredo = 0;
/*pr_info("unredirect %d.%d\n", port->dev->nr, port->nr);*/
/*pr_info("DDBridge: unredirect %d.%d\n", port->dev->nr, port->nr);*/
mutex_lock(&redirect_lock);
if (port->output->dma->running) {
mutex_unlock(&redirect_lock);
@@ -579,6 +632,29 @@ static void ddb_buffers_free(struct ddb *dev)
}
}
/*
* Control:
*
* Bit 0 - Enable TS
* 1 - Reset
* 2 - clock enable
* 3 - clock phase
* 4 - gap enable
* 5 - send null packets on underrun
* 6 - enable clock gating
* 7 - set error bit on inserted null packets
* 8-10 - fine adjust clock delay
* 11- HS (high speed), if NCO mode=0: 0=72MHz 1=96Mhz
* 12- enable NCO mode
*
* Control 2:
*
* Bit 0-6 : gap_size, Gap = (gap_size * 2) + 4
* 16-31: HS = 0: Speed = 72 * Value / 8192 MBit/s
* HS = 1: Speed = 72 * 8 / (Value + 1) MBit/s (only bit 19-16 used)
*
*/
static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
{
struct ddb *dev = output->port->dev;
@@ -981,7 +1057,7 @@ static u32 ddb_input_avail(struct ddb_input *input)
off = (stat & 0x7ff) << 7;
if (ctrl & 4) {
pr_err("IA %d %d %08x\n", idx, off, ctrl);
pr_err("DDBridge: IA %d %d %08x\n", idx, off, ctrl);
ddbwritel(dev, stat, DMA_BUFFER_ACK(input->dma));
return 0;
}
@@ -1259,7 +1335,7 @@ static int demod_attach_drxk(struct ddb_input *input)
i2c, 0x29 + (input->nr & 1),
&dvb->fe2);
if (!fe) {
pr_err("No DRXK found!\n");
pr_err("DDBridge: No DRXK found!\n");
return -ENODEV;
}
fe->sec_priv = input;
@@ -1269,42 +1345,21 @@ static int demod_attach_drxk(struct ddb_input *input)
}
#endif
struct cxd2843_cfg cxd2843_0 = {
.adr = 0x6c,
.ts_clock = 1,
};
struct cxd2843_cfg cxd2843_1 = {
.adr = 0x6d,
.ts_clock = 1,
};
struct cxd2843_cfg cxd2843p_0 = {
.adr = 0x6c,
.parallel = 1,
};
struct cxd2843_cfg cxd2843p_1 = {
.adr = 0x6d,
.parallel = 1,
};
static int demod_attach_cxd2843(struct ddb_input *input, int par)
static int demod_attach_cxd2843(struct ddb_input *input, int par, int osc24)
{
struct i2c_adapter *i2c = &input->port->i2c->adap;
struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
struct dvb_frontend *fe;
struct cxd2843_cfg cfg;
cfg.adr = (input->nr & 1) ? 0x6d : 0x6c;
cfg.ts_clock = par ? 0 : 1;
cfg.parallel = par ? 1 : 0;
cfg.osc = osc24 ? 24000000 : 20500000;
fe = dvb->fe = dvb_attach(cxd2843_attach, i2c, &cfg);
if (par)
fe = dvb->fe = dvb_attach(cxd2843_attach, i2c,
(input->nr & 1) ?
&cxd2843p_1 : &cxd2843p_0);
else
fe = dvb->fe = dvb_attach(cxd2843_attach, i2c,
(input->nr & 1) ?
&cxd2843_1 : &cxd2843_0);
if (!dvb->fe) {
pr_err("No cxd2837/38/43 found!\n");
pr_err("DDBridge: No cxd2837/38/43/54 found!\n");
return -ENODEV;
}
fe->sec_priv = input;
@@ -1327,7 +1382,7 @@ static int demod_attach_stv0367dd(struct ddb_input *input)
&cfg,
&dvb->fe2);
if (!dvb->fe) {
pr_err("No stv0367 found!\n");
pr_err("DDBridge: No stv0367 found!\n");
return -ENODEV;
}
fe->sec_priv = input;
@@ -1348,7 +1403,7 @@ static int tuner_attach_tda18271(struct ddb_input *input)
if (dvb->fe->ops.i2c_gate_ctrl)
dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 0);
if (!fe) {
pr_err("No TDA18271 found!\n");
pr_err("DDBridge: No TDA18271 found!\n");
return -ENODEV;
}
return 0;
@@ -1363,7 +1418,7 @@ static int tuner_attach_tda18212dd(struct ddb_input *input)
fe = dvb_attach(tda18212dd_attach, dvb->fe, i2c,
(input->nr & 1) ? 0x63 : 0x60);
if (!fe) {
pr_err("No TDA18212 found!\n");
pr_err("DDBridge: No TDA18212 found!\n");
return -ENODEV;
}
return 0;
@@ -1388,7 +1443,7 @@ static int tuner_attach_tda18212(struct ddb_input *input)
cfg = (input->nr & 1) ? &tda18212_1 : &tda18212_0;
fe = dvb_attach(tda18212_attach, dvb->fe, i2c, cfg);
if (!fe) {
pr_err("No TDA18212 found!\n");
pr_err("DDBridge: No TDA18212 found!\n");
return -ENODEV;
}
return 0;
@@ -1465,13 +1520,13 @@ static int demod_attach_stv0900(struct ddb_input *input, int type)
(input->nr & 1) ? STV090x_DEMODULATOR_1
: STV090x_DEMODULATOR_0);
if (!dvb->fe) {
pr_err("No STV0900 found!\n");
pr_err("DDBridge: No STV0900 found!\n");
return -ENODEV;
}
if (!dvb_attach(lnbh24_attach, dvb->fe, i2c, 0,
0, (input->nr & 1) ?
(0x09 - type) : (0x0b - type))) {
pr_err("No LNBH24 found!\n");
pr_err("DDBridge: No LNBH24 found!\n");
return -ENODEV;
}
return 0;
@@ -1488,10 +1543,10 @@ static int tuner_attach_stv6110(struct ddb_input *input, int type)
ctl = dvb_attach(stv6110x_attach, dvb->fe, tunerconf, i2c);
if (!ctl) {
pr_err("No STV6110X found!\n");
pr_err("DDBridge: No STV6110X found!\n");
return -ENODEV;
}
pr_info("attach tuner input %d adr %02x\n",
pr_info("DDBridge: attach tuner input %d adr %02x\n",
input->nr, tunerconf->addr);
feconf->tuner_init = ctl->tuner_init;
@@ -1522,6 +1577,8 @@ static int demod_attach_stv0910(struct ddb_input *input, int type)
struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
struct stv0910_cfg cfg = stv0910_p;
if (stv0910_single)
cfg.single = 1;
if (type)
cfg.parallel = 2;
dvb->fe = dvb_attach(stv0910_attach, i2c, &cfg, (input->nr & 1));
@@ -1531,14 +1588,14 @@ static int demod_attach_stv0910(struct ddb_input *input, int type)
&cfg, (input->nr & 1));
}
if (!dvb->fe) {
pr_err("No STV0910 found!\n");
pr_err("DDBridge: No STV0910 found!\n");
return -ENODEV;
}
if (!dvb_attach(lnbh25_attach, dvb->fe, i2c,
((input->nr & 1) ? 0x0d : 0x0c))) {
if (!dvb_attach(lnbh25_attach, dvb->fe, i2c,
((input->nr & 1) ? 0x09 : 0x08))) {
pr_err("No LNBH25 found!\n");
pr_err("DDBridge: No LNBH25 found!\n");
return -ENODEV;
}
}
@@ -1556,7 +1613,7 @@ static int tuner_attach_stv6111(struct ddb_input *input, int type)
if (!fe) {
fe = dvb_attach(stv6111_attach, dvb->fe, i2c, adr & ~4);
if (!fe) {
pr_err("No STV6111 found at 0x%02x!\n", adr);
pr_err("DDBridge: No STV6111 found at 0x%02x!\n", adr);
return -ENODEV;
}
}
@@ -1578,7 +1635,7 @@ static int lnb_command(struct ddb *dev, u32 link, u32 lnb, u32 cmd)
msleep(20);
}
if (c == 10)
pr_info("lnb_command lnb = %08x cmd = %08x\n", lnb, cmd);
pr_info("DDBridge: lnb_command lnb = %08x cmd = %08x\n", lnb, cmd);
return 0;
}
@@ -1845,7 +1902,7 @@ static int mxl_fw_read(void *priv, u8 *buf, u32 len)
struct ddb_link *link = priv;
struct ddb *dev = link->dev;
pr_info("Read mxl_fw from link %u\n", link->nr);
pr_info("DDBridge: Read mxl_fw from link %u\n", link->nr);
return ddbridge_flashread(dev, link->nr, buf, 0xc0000, len);
}
@@ -1856,7 +1913,7 @@ static int lnb_init_fmode(struct ddb *dev, struct ddb_link *link, u32 fm)
if (link->lnb.fmode == fm)
return 0;
pr_info("Set fmode link %u = %u\n", l, fm);
pr_info("DDBridge: Set fmode link %u = %u\n", l, fm);
mutex_lock(&link->lnb.lock);
if (fm == 2 || fm == 1) {
lnb_set_tone(dev, l, 0, SEC_TONE_OFF);
@@ -1904,7 +1961,7 @@ static int fe_attach_mxl5xx(struct ddb_input *input)
tuner = 0;
dvb->fe = dvb_attach(mxl5xx_attach, i2c, &cfg, demod, tuner);
if (!dvb->fe) {
pr_err("No MXL5XX found!\n");
pr_err("DDBridge: No MXL5XX found!\n");
return -ENODEV;
}
if (input->nr < 4) {
@@ -2161,7 +2218,7 @@ static int dvb_input_attach(struct ddb_input *input)
struct ddb_port *port = input->port;
struct dvb_adapter *adap = dvb->adap;
struct dvb_demux *dvbdemux = &dvb->demux;
int par = 0;
int par = 0, osc24 = 0;
dvb->attached = 0x01;
@@ -2241,6 +2298,12 @@ static int dvb_input_attach(struct ddb_input *input)
if (tuner_attach_tda18212dd(input) < 0)
return -ENODEV;
break;
case DDB_TUNER_DVBC2T2I_SONY_P:
if (input->port->dev->link[input->port->lnr].info->ts_quirks &
TS_QUIRK_ALT_OSC)
osc24 = 0;
else
osc24 = 1;
case DDB_TUNER_DVBCT2_SONY_P:
case DDB_TUNER_DVBC2T2_SONY_P:
case DDB_TUNER_ISDBT_SONY_P:
@@ -2249,10 +2312,17 @@ static int dvb_input_attach(struct ddb_input *input)
par = 0;
else
par = 1;
if (demod_attach_cxd2843(input, par, osc24) < 0)
return -ENODEV;
if (tuner_attach_tda18212dd(input) < 0)
return -ENODEV;
break;
case DDB_TUNER_DVBC2T2I_SONY:
osc24 = 1;
case DDB_TUNER_DVBCT2_SONY:
case DDB_TUNER_DVBC2T2_SONY:
case DDB_TUNER_ISDBT_SONY:
if (demod_attach_cxd2843(input, par) < 0)
if (demod_attach_cxd2843(input, 0, osc24) < 0)
return -ENODEV;
if (tuner_attach_tda18212dd(input) < 0)
return -ENODEV;
@@ -2284,7 +2354,7 @@ static int port_has_encti(struct ddb_port *port)
int ret = i2c_read_reg(&port->i2c->adap, 0x20, 0, &val);
if (!ret)
pr_info("[0x20]=0x%02x\n", val);
pr_info("DDBridge: [0x20]=0x%02x\n", val);
return ret ? 0 : 1;
}
@@ -2380,7 +2450,7 @@ static int init_xo2(struct ddb_port *port)
return res;
if (data[0] != 0x01) {
pr_info("Port %d: invalid XO2\n", port->nr);
pr_info("DDBridge: Port %d: invalid XO2\n", port->nr);
return -1;
}
@@ -2399,7 +2469,7 @@ static int init_xo2(struct ddb_port *port)
i2c_write_reg(i2c, 0x10, 0x09, xo2_speed);
if (dev->link[port->lnr].info->con_clock) {
pr_info("Setting continuous clock for XO2\n");
pr_info("DDBridge: Setting continuous clock for XO2\n");
i2c_write_reg(i2c, 0x10, 0x0a, 0x03);
i2c_write_reg(i2c, 0x10, 0x0b, 0x03);
} else {
@@ -2426,11 +2496,11 @@ static int init_xo2_ci(struct ddb_port *port)
return res;
if (data[0] > 1) {
pr_info("Port %d: invalid XO2 CI %02x\n",
pr_info("DDBridge: Port %d: invalid XO2 CI %02x\n",
port->nr, data[0]);
return -1;
}
pr_info("Port %d: DuoFlex CI %u.%u\n", port->nr, data[0], data[1]);
pr_info("DDBridge: Port %d: DuoFlex CI %u.%u\n", port->nr, data[0], data[1]);
i2c_read_reg(i2c, 0x10, 0x08, &val);
if (val != 0) {
@@ -2449,7 +2519,7 @@ static int init_xo2_ci(struct ddb_port *port)
usleep_range(2000, 3000);
if (dev->link[port->lnr].info->con_clock) {
pr_info("Setting continuous clock for DuoFLex CI\n");
pr_info("DDBridge: Setting continuous clock for DuoFLex CI\n");
i2c_write_reg(i2c, 0x10, 0x0a, 0x03);
i2c_write_reg(i2c, 0x10, 0x0b, 0x03);
} else {
@@ -2476,14 +2546,14 @@ static int port_has_cxd28xx(struct ddb_port *port, u8 *id)
static char *xo2names[] = {
"DUAL DVB-S2", "DUAL DVB-C/T/T2",
"DUAL DVB-ISDBT", "DUAL DVB-C/C2/T/T2",
"DUAL ATSC", "DUAL DVB-C/C2/T/T2",
"DUAL ATSC", "DUAL DVB-C/C2/T/T2,ISDB-T",
"", ""
};
static char *xo2types[] = {
"DVBS_ST", "DVBCT2_SONY",
"ISDBT_SONY", "DVBC2T2_SONY",
"ATSC_ST", "DVBC2T2_ST"
"ATSC_ST", "DVBC2T2I_SONY"
};
static void ddb_port_probe(struct ddb_port *port)
@@ -2558,13 +2628,13 @@ static void ddb_port_probe(struct ddb_port *port)
ddbwritel(dev, I2C_SPEED_400,
port->i2c->regs + I2C_TIMING);
} else {
pr_info(KERN_INFO "Port %d: Uninitialized DuoFlex\n",
pr_info(KERN_INFO "DDBridge: Port %d: Uninitialized DuoFlex\n",
port->nr);
return;
}
} else if (port_has_xo2(port, &type, &id)) {
ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
/*pr_info("XO2 ID %02x\n", id);*/
pr_info("DDBridge: XO2 ID %02x\n", id);
if (type == 2) {
port->name = "DuoFlex CI";
port->class = DDB_PORT_CI;
@@ -2601,6 +2671,11 @@ static void ddb_port_probe(struct ddb_port *port)
port->type = DDB_TUNER_ISDBT_SONY_P;
port->type_name = "ISDBT_SONY";
break;
case 0xc1:
port->name = "DUAL DVB-C2T2 ISDB-T CXD2854";
port->type = DDB_TUNER_DVBC2T2_SONY_P;
port->type_name = "DVBC2T2_ISDBT_SONY";
break;
default:
return;
}
@@ -2861,7 +2936,7 @@ static int slot_reset_xo2(struct dvb_ca_en50221 *ca, int slot)
{
struct ddb_ci *ci = ca->data;
pr_info("%s\n", __func__);
pr_info("DDBridge: %s\n", __func__);
write_creg(ci, 0x01, 0x01);
write_creg(ci, 0x04, 0x04);
msleep(20);
@@ -2875,7 +2950,7 @@ static int slot_shutdown_xo2(struct dvb_ca_en50221 *ca, int slot)
{
struct ddb_ci *ci = ca->data;
pr_info("%s\n", __func__);
pr_info("DDBridge: %s\n", __func__);
/*i2c_write_reg(i2c, adr, 0x03, 0x60);*/
/*i2c_write_reg(i2c, adr, 0x00, 0xc0);*/
write_creg(ci, 0x10, 0xff);
@@ -2887,7 +2962,7 @@ static int slot_ts_enable_xo2(struct dvb_ca_en50221 *ca, int slot)
{
struct ddb_ci *ci = ca->data;
pr_info("%s\n", __func__);
pr_info("DDBridge: %s\n", __func__);
write_creg(ci, 0x00, 0x10);
return 0;
}
@@ -3017,7 +3092,7 @@ static int ddb_port_attach(struct ddb_port *port)
break;
}
if (ret < 0)
pr_err("port_attach on port %d failed\n", port->nr);
pr_err("DDBridge: port_attach on port %d failed\n", port->nr);
return ret;
}
@@ -3029,12 +3104,12 @@ static int ddb_ports_attach(struct ddb *dev)
dev->ns_num = dev->link[0].info->ns_num;
for (i = 0; i < dev->ns_num; i++)
dev->ns[i].nr = i;
pr_info("%d netstream channels\n", dev->ns_num);
pr_info("DDBridge: %d netstream channels\n", dev->ns_num);
if (dev->port_num) {
ret = dvb_register_adapters(dev);
if (ret < 0) {
pr_err("Registering adapters failed. Check DVB_MAX_ADAPTERS in config.\n");
pr_err("DDBridge: Registering adapters failed. Check DVB_MAX_ADAPTERS in config.\n");
return ret;
}
}
@@ -3118,14 +3193,14 @@ static void input_write_dvb(struct ddb_input *input,
while (dma->cbuf != ((dma->stat >> 11) & 0x1f)
|| (4 & dma->ctrl)) {
if (4 & dma->ctrl) {
/*pr_err("Overflow dma %d\n", dma->nr);*/
/*pr_err("DDBridge: Overflow dma %d\n", dma->nr);*/
ack = 1;
}
if (alt_dma)
dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf],
dma2->size, DMA_FROM_DEVICE);
#if 0
pr_info("%02x %02x %02x %02x \n",
pr_info("DDBridge: %02x %02x %02x %02x \n",
dma2->vbuf[dma->cbuf][0], dma2->vbuf[dma->cbuf][1],
dma2->vbuf[dma->cbuf][2], dma2->vbuf[dma->cbuf][3]);
#endif
@@ -3165,7 +3240,7 @@ static void input_tasklet(unsigned long data)
#if 0
if (4 & dma->ctrl)
pr_err("Overflow dma %d\n", dma->nr);
pr_err("DDBridge: Overflow dma %d\n", dma->nr);
#endif
if (input->redi)
input_write_dvb(input, input->redi);
@@ -3263,8 +3338,8 @@ static void ddb_dma_init(struct ddb_io *io, int nr, int out)
dma->div = INPUT_DMA_IRQ_DIV;
}
ddbwritel(io->port->dev, 0, DMA_BUFFER_ACK(dma));
pr_info("init link %u, io %u, dma %u, dmaregs %08x bufregs %08x\n",
io->port->lnr, io->nr, nr, dma->regs, dma->bufregs);
pr_debug("DDBridge: init link %u, io %u, dma %u, dmaregs %08x bufregs %08x\n",
io->port->lnr, io->nr, nr, dma->regs, dma->bufregs);
}
static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
@@ -3279,7 +3354,7 @@ static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
rm = io_regmap(input, 1);
input->regs = DDB_LINK_TAG(port->lnr) |
(rm->input->base + rm->input->size * nr);
pr_info("init link %u, input %u, regs %08x\n", port->lnr, nr, input->regs);
pr_debug("DDBridge: init link %u, input %u, regs %08x\n", port->lnr, nr, input->regs);
if (dev->has_dma) {
struct ddb_regmap *rm0 = io_regmap(input, 0);
u32 base = rm0->irq_base_idma;
@@ -3288,7 +3363,8 @@ static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
if (port->lnr)
dma_nr += 32 + (port->lnr - 1) * 8;
pr_info("init link %u, input %u, handler %u\n", port->lnr, nr, dma_nr + base);
pr_debug("DDBridge: init link %u, input %u, handler %u\n",
port->lnr, nr, dma_nr + base);
dev->handler[0][dma_nr + base] = input_handler;
dev->handler_data[0][dma_nr + base] = (unsigned long) input;
ddb_dma_init(input, dma_nr, 0);
@@ -3307,7 +3383,8 @@ static void ddb_output_init(struct ddb_port *port, int nr)
rm = io_regmap(output, 1);
output->regs = DDB_LINK_TAG(port->lnr) |
(rm->output->base + rm->output->size * nr);
pr_info("init link %u, output %u, regs %08x\n", port->lnr, nr, output->regs);
pr_debug("DDBridge: init link %u, output %u, regs %08x\n",
port->lnr, nr, output->regs);
if (dev->has_dma) {
struct ddb_regmap *rm0 = io_regmap(output, 0);
u32 base = rm0->irq_base_odma;
@@ -3385,7 +3462,7 @@ static void ddb_ports_init(struct ddb *dev)
port->name = "DuoFlex CI_B";
port->i2c = dev->port[p - 1].i2c;
}
pr_info("Port %u: Link %u, Link Port %u (TAB %u): %s\n",
pr_info("DDBridge: Port %u: Link %u, Link Port %u (TAB %u): %s\n",
port->pnr, port->lnr, port->nr,
port->nr + 1, port->name);
@@ -3682,7 +3759,7 @@ static irqreturn_t irq_thread(int irq, void *dev_id)
{
/* struct ddb *dev = (struct ddb *) dev_id; */
/*pr_info("%s\n", __func__);*/
/*pr_info("DDBridge: %s\n", __func__);*/
return IRQ_HANDLED;
}
@@ -3749,9 +3826,9 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
return -EINVAL;
ctrl = (input->port->lnr << 16) | ((input->nr & 7) << 8) |
((ts->filter_mask & 3) << 2);
/*pr_info("GET_TS %u.%u\n", input->port->lnr, input->nr);*/
/*pr_info("DDBridge: GET_TS %u.%u\n", input->port->lnr, input->nr);*/
if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) {
pr_info("ts capture busy\n");
pr_info("DDBridge: ts capture busy\n");
return -EBUSY;
}
ddb_dvb_ns_input_start(input);
@@ -3785,7 +3862,7 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
if (ctrl & 1)
return -EBUSY;
if (ctrl & (1 << 14)) {
/*pr_info("ts capture timeout\n");*/
/*pr_info("DDBridge: ts capture timeout\n");*/
return -EAGAIN;
}
ddbcpyfrom(dev, dev->tsbuf, TS_CAPTURE_MEMORY,
@@ -3799,10 +3876,10 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
{
u32 ctrl = 0;
/*pr_info("cancel ts capture: 0x%x\n", ctrl);*/
/*pr_info("DDBridge: cancel ts capture: 0x%x\n", ctrl);*/
ddbwritel(dev, ctrl, TS_CAPTURE_CONTROL);
ctrl = ddbreadl(dev, TS_CAPTURE_CONTROL);
/*pr_info("control register is 0x%x\n", ctrl);*/
/*pr_info("DDBridge: control register is 0x%x\n", ctrl);*/
break;
}
case NSD_STOP_GET_TS:
@@ -3814,10 +3891,10 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
if (!input)
return -EINVAL;
if (ctrl & 1) {
pr_info("cannot stop ts capture, while it was neither finished nor canceled\n");
pr_info("DDBridge: cannot stop ts capture, while it was neither finished nor canceled\n");
return -EBUSY;
}
/*pr_info("ts capture stopped\n");*/
/*pr_info("DDBridge: ts capture stopped\n");*/
ddb_dvb_ns_input_stop(input);
break;
}
@@ -4359,24 +4436,37 @@ static ssize_t fan_store(struct device *device, struct device_attribute *d,
return count;
}
static ssize_t fanspeed_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct ddb *dev = dev_get_drvdata(device);
int num = attr->attr.name[8] - 0x30;
struct ddb_link *link = &dev->link[num];
u32 spd;
spd = ddblreadl(link, TEMPMON_FANCONTROL) & 0xff;
return sprintf(buf, "%u\n", spd * 100);
}
static ssize_t temp_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct ddb *dev = dev_get_drvdata(device);
struct ddb_link *link = &dev->link[0];
struct i2c_adapter *adap;
s32 temp, temp2, temp3;
int i;
u8 tmp[2];
if (dev->link[0].info->type == DDB_MOD) {
if (dev->link[0].info->version == 2) {
temp = ddbreadl(dev, TEMPMON2_BOARD);
temp = 0xffff & ddbreadl(dev, TEMPMON2_BOARD);
temp = (temp * 1000) >> 8;
temp2 = ddbreadl(dev, TEMPMON2_FPGACORE);
temp2 = 0xffff & ddbreadl(dev, TEMPMON2_FPGACORE);
temp2 = (temp2 * 1000) >> 8;
temp3 = ddbreadl(dev, TEMPMON2_QAMCORE);
temp3 = 0xffff & ddbreadl(dev, TEMPMON2_QAMCORE);
temp3 = (temp3 * 1000) >> 8;
return sprintf(buf, "%d %d %d\n", temp, temp2, temp3);
@@ -4491,7 +4581,7 @@ static void ddb_set_led(struct ddb *dev, int num, int val)
i2c_write_reg16(&dev->i2c[num].adap,
0x1f, 0xf00f, val ? 1 : 0);
break;
case DDB_TUNER_XO2 ... DDB_TUNER_DVBC2T2_ST:
case DDB_TUNER_XO2 ... DDB_TUNER_DVBC2T2I_SONY:
{
u8 v;
@@ -4613,7 +4703,7 @@ static ssize_t redirect_store(struct device *device,
res = ddb_redirect(i, p);
if (res < 0)
return res;
pr_info("redirect: %02x, %02x\n", i, p);
pr_info("DDBridge: redirect: %02x, %02x\n", i, p);
return count;
}
@@ -4637,7 +4727,7 @@ static ssize_t redirect2_store(struct device *device,
res = ddb_redirect(i, p);
if (res < 0)
return res;
pr_info("redirect: %02x, %02x\n", i, p);
pr_info("DDBridge: redirect: %02x, %02x\n", i, p);
return count;
}
@@ -4849,6 +4939,13 @@ static struct device_attribute ddb_attrs_led[] = {
__ATTR(led3, 0664, led_show, led_store),
};
static struct device_attribute ddb_attrs_fanspeed[] = {
__ATTR_MRO(fanspeed0, fanspeed_show),
__ATTR_MRO(fanspeed1, fanspeed_show),
__ATTR_MRO(fanspeed2, fanspeed_show),
__ATTR_MRO(fanspeed3, fanspeed_show),
};
static struct class ddb_class = {
.name = "ddbridge",
.owner = THIS_MODULE,
@@ -4878,6 +4975,10 @@ static void ddb_device_attrs_del(struct ddb *dev)
{
int i;
for (i = 0; i < 4; i++)
if (dev->link[i].info &&
dev->link[i].info->tempmon_irq)
device_remove_file(dev->ddb_dev, &ddb_attrs_fanspeed[i]);
for (i = 0; i < dev->link[0].info->temp_num; i++)
device_remove_file(dev->ddb_dev, &ddb_attrs_temp[i]);
for (i = 0; i < dev->link[0].info->port_num; i++)
@@ -4920,6 +5021,12 @@ static int ddb_device_attrs_add(struct ddb *dev)
&ddb_attrs_led[i]))
goto fail;
}
for (i = 0; i < 4; i++)
if (dev->link[i].info &&
dev->link[i].info->tempmon_irq)
if (device_create_file(dev->ddb_dev,
&ddb_attrs_fanspeed[i]))
goto fail;
return 0;
fail:
return -1;
@@ -4939,7 +5046,7 @@ static int ddb_device_create(struct ddb *dev)
dev, "ddbridge%d", dev->nr);
if (IS_ERR(dev->ddb_dev)) {
res = PTR_ERR(dev->ddb_dev);
pr_info("Could not create ddbridge%d\n", dev->nr);
pr_info("DDBridge: Could not create ddbridge%d\n", dev->nr);
goto fail;
}
res = ddb_device_attrs_add(dev);
@@ -4973,7 +5080,7 @@ static void gtl_link_handler(unsigned long priv)
struct ddb *dev = (struct ddb *) priv;
u32 regs = dev->link[0].info->regmap->gtl->base;
pr_info("GT link change: %u\n",
pr_info("DDBridge: GT link change: %u\n",
(1 & ddbreadl(dev, regs)));
}
@@ -4985,7 +5092,7 @@ static void link_tasklet(unsigned long data)
u32 l = link->nr;
s = ddbreadl(dev, tag | INTERRUPT_STATUS);
pr_info("gtl_irq %08x = %08x\n", tag | INTERRUPT_STATUS, s);
pr_info("DDBridge: gtl_irq %08x = %08x\n", tag | INTERRUPT_STATUS, s);
if (!s)
return;
@@ -4994,6 +5101,7 @@ static void link_tasklet(unsigned long data)
LINK_IRQ_HANDLE(l, 1);
LINK_IRQ_HANDLE(l, 2);
LINK_IRQ_HANDLE(l, 3);
LINK_IRQ_HANDLE(l, 24);
}
static void gtl_irq_handler(unsigned long priv)
@@ -5005,11 +5113,12 @@ static void gtl_irq_handler(unsigned long priv)
while ((s = ddbreadl(dev, tag | INTERRUPT_STATUS))) {
ddbwritel(dev, s, tag | INTERRUPT_ACK);
//pr_info("gtlirq %08x\n", s);
//pr_info("DDBridge: gtlirq %08x\n", s);
LINK_IRQ_HANDLE(l, 0);
LINK_IRQ_HANDLE(l, 1);
LINK_IRQ_HANDLE(l, 2);
LINK_IRQ_HANDLE(l, 3);
LINK_IRQ_HANDLE(l, 24);
}
#else
tasklet_schedule(&link->tasklet);
@@ -5021,9 +5130,9 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
struct ddb_link *link = &dev->link[l];
u32 regs = dev->link[0].info->regmap->gtl->base +
(l - 1) * dev->link[0].info->regmap->gtl->size;
u32 id, base = dev->link[0].info->regmap->irq_base_gtl;
u32 id, subid, base = dev->link[0].info->regmap->irq_base_gtl;
pr_info("Checking GT link %u: regs = %08x\n", l, regs);
pr_info("DDBridge: Checking GT link %u: regs = %08x\n", l, regs);
spin_lock_init(&link->lock);
mutex_init(&link->lnb.lock);
@@ -5049,12 +5158,13 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
return -1;
}
id = ddbreadl(dev, DDB_LINK_TAG(l) | 8);
subid = ddbreadl(dev, DDB_LINK_TAG(l) | 12);
switch (id) {
case 0x0007dd01:
link->info = &ddb_s2_48;
break;
case 0x0008dd01:
link->info = &ddb_ct_8;
link->info = &ddb_c2t2_8;
break;
default:
pr_info("DDBridge: Detected GT link but found invalid ID %08x. You might have to update (flash) the add-on card first.",
@@ -5068,16 +5178,24 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
dev->handler_data[0][base + l] = (unsigned long) link;
dev->handler[0][base + l] = gtl_irq_handler;
pr_info("GTL %s\n", dev->link[l].info->name);
pr_info("GTL HW %08x REGMAP %08x\n",
ddbreadl(dev, DDB_LINK_TAG(l) | 0),
ddbreadl(dev, DDB_LINK_TAG(l) | 4));
pr_info("GTL ID %08x\n",
dev->link[l].ids.hwid = ddbreadl(dev, DDB_LINK_TAG(l) | 0);
dev->link[l].ids.regmapid = ddbreadl(dev, DDB_LINK_TAG(l) | 4);
dev->link[l].ids.vendor = id & 0xffff;
dev->link[l].ids.device = id >> 16;
dev->link[l].ids.subvendor = subid & 0xffff;
dev->link[l].ids.subdevice = subid >> 16;
pr_info("DDBridge: GTL %s\n", dev->link[l].info->name);
pr_info("DDBridge: GTL HW %08x REGMAP %08x\n",
dev->link[l].ids.hwid,
dev->link[l].ids.regmapid);
pr_info("DDBridge: GTL ID %08x\n",
ddbreadl(dev, DDB_LINK_TAG(l) | 8));
tasklet_init(&link->tasklet, link_tasklet, (unsigned long) link);
ddbwritel(dev, 0xffffffff, DDB_LINK_TAG(l) | INTERRUPT_ACK);
ddbwritel(dev, 0xf, DDB_LINK_TAG(l) | INTERRUPT_ENABLE);
ddbwritel(dev, 0x0100000f, DDB_LINK_TAG(l) | INTERRUPT_ENABLE);
return 0;
}
@@ -5093,15 +5211,117 @@ static int ddb_gtl_init(struct ddb *dev)
return 0;
}
/****************************************************************************/
/****************************************************************************/
/****************************************************************************/
static void tempmon_setfan(struct ddb_link *link)
{
u32 temp, temp2, pwm;
if ((ddblreadl(link, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) {
pr_info("DDBridge: Over temperature condition\n");
link->OverTemperatureError = 1;
}
temp = (ddblreadl(link, TEMPMON_SENSOR0) >> 8) & 0xFF;
if (temp & 0x80)
temp = 0;
temp2 = (ddblreadl(link, TEMPMON_SENSOR1) >> 8) & 0xFF;
if (temp2 & 0x80)
temp2 = 0;
if (temp2 > temp)
temp = temp2;
pwm = (ddblreadl(link, TEMPMON_FANCONTROL) >> 8) & 0x0F;
if (pwm > 10)
pwm = 10;
if (temp >= link->temp_tab[pwm]) {
while( pwm < 10 && temp >= link->temp_tab[pwm + 1])
pwm += 1;
} else {
while( pwm > 1 && temp < link->temp_tab[pwm - 2])
pwm -= 1;
}
ddblwritel(link, (pwm << 8), TEMPMON_FANCONTROL);
}
static void temp_handler(unsigned long data)
{
struct ddb_link *link = (struct ddb_link *) data;
spin_lock(&link->temp_lock);
tempmon_setfan(link);
spin_unlock(&link->temp_lock);
}
static int tempmon_init(struct ddb_link *link, int FirstTime)
{
struct ddb *dev = link->dev;
int status = 0;
u32 l = link->nr;
spin_lock_irq(&link->temp_lock);
if (FirstTime) {
static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80};
memcpy(link->temp_tab, TemperatureTable, sizeof(TemperatureTable));
}
dev->handler[l][link->info->tempmon_irq] = temp_handler;
dev->handler_data[l][link->info->tempmon_irq] = (unsigned long) link;
ddblwritel(link, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN |
TEMPMON_CONTROL_INTENABLE),
TEMPMON_CONTROL);
ddblwritel(link, (3 << 8), TEMPMON_FANCONTROL);
link->OverTemperatureError =
((ddblreadl(link, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0);
if (link->OverTemperatureError) {
pr_info("DDBridge: Over temperature condition\n");
status = -1;
}
tempmon_setfan(link);
spin_unlock_irq(&link->temp_lock);
return status;
}
static int ddb_init_tempmon(struct ddb_link *link)
{
struct ddb *dev = link->dev;
struct ddb_info *info = link->info;
if (!info->tempmon_irq)
return;
if (info->type == DDB_OCTOPUS_MAX ||
info->type == DDB_OCTOPUS_MAX_CT)
if (link->ids.regmapid < 0x00010002)
return;
spin_lock_init(&link->temp_lock);
printk("init_tempmon\n");
tempmon_init(link, 1);
}
/****************************************************************************/
/****************************************************************************/
/****************************************************************************/
static int ddb_init_boards(struct ddb *dev)
{
struct ddb_info *info;
struct ddb_link *link;
u32 l;
for (l = 0; l < DDB_MAX_LINK; l++) {
info = dev->link[l].info;
link = &dev->link[l];
info = link->info;
if (!info)
continue;
pr_info("DDBridge: link %u vendor %04x device %04x subvendor %04x subdevice %04x\n",
l,
dev->link[l].ids.vendor, dev->link[l].ids.device,
dev->link[l].ids.subvendor, dev->link[l].ids.subdevice);
if (info->board_control) {
ddbwritel(dev, 0, DDB_LINK_TAG(l) | BOARD_CONTROL);
msleep(100);
@@ -5113,6 +5333,7 @@ static int ddb_init_boards(struct ddb *dev)
DDB_LINK_TAG(l) | BOARD_CONTROL);
usleep_range(2000, 3000);
}
ddb_init_tempmon(link);
}
return 0;
}
@@ -5140,7 +5361,7 @@ static int ddb_init(struct ddb *dev)
goto fail;
ddb_ports_init(dev);
if (ddb_buffers_alloc(dev) < 0) {
pr_info(": Could not allocate buffer memory\n");
pr_info("DDBridge: Could not allocate buffer memory\n");
goto fail2;
}
#if 0
@@ -5163,14 +5384,14 @@ static int ddb_init(struct ddb *dev)
fail3:
ddb_ports_detach(dev);
pr_err("fail3\n");
pr_err("DDBridge: fail3\n");
ddb_ports_release(dev);
fail2:
pr_err("fail2\n");
pr_err("DDBridge: fail2\n");
ddb_buffers_free(dev);
ddb_i2c_release(dev);
fail:
pr_err("fail1\n");
pr_err("DDBridge: fail1\n");
return -1;
}

2
ddbridge/ddbridge-i2c.c
View File

@@ -115,7 +115,7 @@ static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
stat = wait_for_completion_timeout(&i2c->completion, HZ);
val = ddbreadl(dev, i2c->regs + I2C_COMMAND);
if (stat == 0) {
pr_err("DDBridge I2C timeout, card %d, port %d, link %u\n",
pr_err("DDBridge: I2C timeout, card %d, port %d, link %u\n",
dev->nr, i2c->nr, i2c->link);
#if 1
{

511
ddbridge/ddbridge-mod.c
View File

@@ -182,7 +182,7 @@ void ddbridge_mod_output_stop(struct ddb_output *output)
ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
#endif
mod_busy(dev, output->nr);
pr_info("mod_output_stop %d.%d\n", dev->nr, output->nr);
pr_info("DDBridge: mod_output_stop %d.%d\n", dev->nr, output->nr);
}
static void mod_set_incs(struct ddb_output *output)
@@ -213,15 +213,103 @@ static void mod_set_rateinc(struct ddb *dev, u32 chan)
mod_busy(dev, chan);
}
static void mod_calc_rateinc(struct ddb_mod *mod)
{
u32 ri;
pr_info("DDBridge: ibitrate %llu\n", mod->ibitrate);
pr_info("DDBridge: obitrate %llu\n", mod->obitrate);
if (mod->ibitrate != 0) {
u64 d = mod->obitrate - mod->ibitrate;
d = div64_u64(d, mod->obitrate >> 24);
if (d > 0xfffffe)
ri = 0xfffffe;
else
ri = d;
} else
ri = 0;
mod->rate_inc = ri;
pr_info("DDBridge: ibr=%llu, obr=%llu, ri=0x%06x\n",
mod->ibitrate >> 32, mod->obitrate >> 32, ri);
}
static int mod_calc_obitrate(struct ddb_mod *mod)
{
struct ddb *dev = mod->port->dev;
u64 ofac;
ofac = (((u64) mod->symbolrate) << 32) * 188;
ofac = div_u64(ofac, 204);
mod->obitrate = ofac * (mod->modulation + 3);
return 0;
}
static int mod_set_symbolrate(struct ddb_mod *mod, u32 srate)
{
struct ddb *dev = mod->port->dev;
u64 ofac;
if (dev->link[0].info->version < 2) {
if (srate != 6900000)
return -EINVAL;
} else {
if (srate > 7100000)
return -EINVAL;
}
mod->symbolrate = srate;
mod_calc_obitrate(mod);
return 0;
}
static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 };
void ddbridge_mod_output_start(struct ddb_output *output)
static int mod_set_modulation(struct ddb_mod *mod, enum fe_modulation modulation)
{
struct ddb *dev = mod->port->dev;
u64 ofac;
if (modulation > QAM_256 || modulation < QAM_16)
return -EINVAL;
mod->modulation = modulation;
if (dev->link[0].info->version < 2)
ddbwritel(dev, qamtab[modulation], CHANNEL_SETTINGS(mod->nr));
mod_calc_obitrate(mod);
return 0;
}
static int mod_set_frequency(struct ddb_mod *mod, u32 frequency)
{
u32 freq = frequency / 1000000;
if (frequency % 1000000)
return -EINVAL;
if ((freq - 114) % 8)
return -EINVAL;
if ((freq < 114) || (freq > 874))
return -EINVAL;
mod->frequency = frequency;
return 0;
}
static int mod_set_ibitrate(struct ddb_mod *mod, u64 ibitrate)
{
if (ibitrate > mod->obitrate)
return -EINVAL;
mod->ibitrate = ibitrate;
mod_calc_rateinc(mod);
return 0;
}
int ddbridge_mod_output_start(struct ddb_output *output)
{
struct ddb *dev = output->port->dev;
u32 Channel = output->nr;
struct ddb_mod *mod = &dev->mod[output->nr];
u32 Symbolrate = 6900000;
u32 Symbolrate = mod->symbolrate;
mod_calc_rateinc(mod);
/*PCRIncrement = RoundPCR(PCRIncrement);*/
/*PCRDecrement = RoundPCR(PCRDecrement);*/
@@ -247,17 +335,17 @@ void ddbridge_mod_output_start(struct ddb_output *output)
udelay(10);
ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
pr_info("CHANNEL_BASE = %08x\n", CHANNEL_BASE);
pr_info("CHANNEL_CONTROL = %08x\n", CHANNEL_CONTROL(Channel));
pr_info("DDBridge: CHANNEL_BASE = %08x\n", CHANNEL_BASE);
pr_info("DDBridge: CHANNEL_CONTROL = %08x\n", CHANNEL_CONTROL(Channel));
if (dev->link[0].info->version == 2) {
u32 Output = ((dev->mod_base.frequency - 114000000)/8000000 + Channel) % 96;
//u32 Output = ((dev->mod_base.frequency - 114000000)/8000000 + Channel) % 96;
u32 Output = (mod->frequency - 114000000) / 8000000;
u32 KF = Symbolrate;
u32 LF = 9000000UL;
u32 d = gcd(KF,LF);
u32 checkLF;
mod->modulation = QAM_256 - 1;
ddbwritel(dev, mod->modulation, CHANNEL_SETTINGS(Channel));
ddbwritel(dev, mod->modulation - 1, CHANNEL_SETTINGS(Channel));
ddbwritel(dev, Output, CHANNEL_SETTINGS2(Channel));
KF = KF / d;
@@ -274,7 +362,7 @@ void ddbridge_mod_output_start(struct ddb_output *output)
if (checkLF <= 1)
return -EINVAL;
pr_info("KF=%u LF=%u Output=%u mod=%u\n", KF, LF, Output, mod->modulation);
pr_info("DDBridge: KF=%u LF=%u Output=%u mod=%u\n", KF, LF, Output, mod->modulation);
ddbwritel(dev, KF, CHANNEL_KF(Channel));
ddbwritel(dev, LF, CHANNEL_LF(Channel));
@@ -296,7 +384,8 @@ void ddbridge_mod_output_start(struct ddb_output *output)
if (dev->link[0].info->version == 2)
if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_UNMUTE))
return -EINVAL;
pr_info("mod_output_start %d.%d\n", dev->nr, output->nr);
pr_info("DDBridge: mod_output_start %d.%d\n", dev->nr, output->nr);
return 0;
}
/****************************************************************************/
@@ -388,7 +477,7 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels
if (MaxUsedChannels == 0)
MaxUsedChannels = (Capacity & FSM_CAPACITY_CUR) >> 16;
pr_info("max used chan = %u\n", MaxUsedChannels);
pr_info("DDBridge: max used chan = %u\n", MaxUsedChannels);
if (MaxUsedChannels <= 1 )
ddbwritel(dev, FSM_GAIN_N1, FSM_GAIN);
else if (MaxUsedChannels <= 2)
@@ -422,14 +511,14 @@ static int mod_get_vga(struct ddb *dev, u32 *pGain)
*pGain = ddbreadl(dev, RF_VGA);
return 0;
}
static void mod_TemperatureMonitorSetFan(struct ddb *dev)
#if 0
static void TemperatureMonitorSetFan(struct ddb *dev)
{
u32 tqam, pwm;
if ((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) {
pr_info("Over temperature condition\n");
dev->mod_base.OverTemperatureError = 1;
pr_info("DDBridge: Over temperature condition\n");
dev->OverTemperatureError = 1;
}
tqam = (ddbreadl(dev, TEMPMON2_QAMCORE) >> 8) & 0xFF;
if (tqam & 0x80)
@@ -439,55 +528,55 @@ static void mod_TemperatureMonitorSetFan(struct ddb *dev)
if (pwm > 10)
pwm = 10;
if (tqam >= dev->mod_base.temp_tab[pwm]) {
while( pwm < 10 && tqam >= dev->mod_base.temp_tab[pwm + 1])
if (tqam >= dev->temp_tab[pwm]) {
while( pwm < 10 && tqam >= dev->temp_tab[pwm + 1])
pwm += 1;
} else {
while( pwm > 1 && tqam < dev->mod_base.temp_tab[pwm - 2])
while( pwm > 1 && tqam < dev->temp_tab[pwm - 2])
pwm -= 1;
}
ddbwritel(dev, (pwm << 8), TEMPMON_FANCONTROL);
}
static void mod_temp_handler(unsigned long data)
static void temp_handler(unsigned long data)
{
struct ddb *dev = (struct ddb *) data;
pr_info("mod_temp_handler\n");
pr_info("DDBridge: temp_handler\n");
spin_lock(&dev->mod_base.temp_lock);
mod_TemperatureMonitorSetFan(dev);
spin_unlock(&dev->mod_base.temp_lock);
spin_lock(&dev->temp_lock);
TemperatureMonitorSetFan(dev);
spin_unlock(&dev->temp_lock);
}
static int mod_TemperatureMonitorInit(struct ddb *dev, int FirstTime) {
static int TemperatureMonitorInit(struct ddb *dev, int FirstTime) {
int status = 0;
spin_lock_irq(&dev->mod_base.temp_lock);
spin_lock_irq(&dev->temp_lock);
if (FirstTime) {
static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80};
memcpy(dev->mod_base.temp_tab, TemperatureTable, sizeof(TemperatureTable));
memcpy(dev->temp_tab, TemperatureTable, sizeof(TemperatureTable));
}
dev->handler[0][8] = mod_temp_handler;
dev->handler[0][8] = temp_handler;
dev->handler_data[0][8] = (unsigned long) dev;
ddbwritel(dev, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN |
TEMPMON_CONTROL_INTENABLE),
TEMPMON_CONTROL);
ddbwritel(dev, (3 << 8), TEMPMON_FANCONTROL);
dev->mod_base.OverTemperatureError =
dev->OverTemperatureError =
((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0);
if (dev->mod_base.OverTemperatureError) {
pr_info("Over temperature condition\n");
if (dev->OverTemperatureError) {
pr_info("DDBridge: Over temperature condition\n");
status = -1;
}
mod_TemperatureMonitorSetFan(dev);
spin_unlock_irq(&dev->mod_base.temp_lock);
TemperatureMonitorSetFan(dev);
spin_unlock_irq(&dev->temp_lock);
return status;
}
#endif
/****************************************************************************/
/****************************************************************************/
/****************************************************************************/
@@ -638,7 +727,7 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
mod_si598_readreg(dev, 11, &Data[4]);
mod_si598_readreg(dev, 12, &Data[5]);
pr_info(" Data = %02x %02x %02x %02x %02x %02x\n",
pr_info("DDBridge: Data = %02x %02x %02x %02x %02x %02x\n",
Data[0], Data[1], Data[2], Data[3], Data[4], Data[5]);
RFreq = (((u64)Data[1] & 0x3F) << 32) | ((u64)Data[2] << 24) |
((u64)Data[3] << 16) | ((u64)Data[4] << 8) |
@@ -652,12 +741,12 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
((u32)(Data[1] & 0xE0) >> 6)) + 1;
fDCO = fOut * (u64)(HSDiv * N);
m_fXtal = fDCO << 28;
pr_info("fxtal %016llx rfreq %016llx\n", m_fXtal, RFreq);
pr_info("DDBridge: fxtal %016llx rfreq %016llx\n", m_fXtal, RFreq);
m_fXtal += RFreq >> 1;
m_fXtal = div64_u64(m_fXtal, RFreq);
pr_info("fOut = %d fXtal = %d fDCO = %d HDIV = %2d, N = %3d\n",
pr_info("DDBridge: fOut = %d fXtal = %d fDCO = %d HDIV = %2d, N = %3d\n",
(u32) fOut, (u32) m_fXtal, (u32) fDCO, (u32) HSDiv, N);
}
@@ -668,7 +757,7 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
if (Div < MinDiv)
Div = Div + 1;
pr_info(" fOut = %u MinDiv = %llu MaxDiv = %llu StartDiv = %llu\n",
pr_info("DDBridge: fOut = %u MinDiv = %llu MaxDiv = %llu StartDiv = %llu\n",
fOut, MinDiv, MaxDiv, Div);
if (Div <= 11) {
@@ -687,7 +776,7 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
if (N > 128)
break;
}
pr_info(" %3d: %llu %llu %llu %u\n",
pr_info("DDBridge: %3d: %llu %llu %llu %u\n",
retry, Div, HSDiv * N, HSDiv, N);
if (HSDiv * N < MinDiv)
Div = Div + 2;
@@ -698,7 +787,7 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
retry = retry - 1;
}
if (retry == 0) {
pr_err(" FAIL\n");
pr_err("DDBridge: FAIL\n");
return -EINVAL;
}
}
@@ -713,16 +802,16 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
fDCO = (u64)fOut * (u64)N * (u64)HSDiv;
pr_info("fdco %16llx\n", fDCO);
pr_info("DDBridge: fdco %16llx\n", fDCO);
RFreq = fDCO<<28;
pr_info("%16llx %16llx\n", fDCO, RFreq);
pr_info("DDBridge: %16llx %16llx\n", fDCO, RFreq);
fxtal = m_fXtal;
do_div(RFreq, fxtal);
pr_info("%16llx %d\n", RFreq, fxtal);
pr_info("DDBridge: %16llx %d\n", RFreq, fxtal);
RF = RFreq;
pr_info("fOut = %u fXtal = %llu fDCO = %llu HSDIV = %llu, N = %u, RFreq = %llu\n",
pr_info("DDBridge: fOut = %u fXtal = %llu fDCO = %llu HSDIV = %llu, N = %u, RFreq = %llu\n",
fOut, m_fXtal, fDCO, HSDiv, N, RFreq);
Data[0] = (u8)(((HSDiv - 4) << 5) | ((N - 1) >> 2));
@@ -732,7 +821,7 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
Data[4] = (u8)((RF >> 8) & 0xFF);
Data[5] = (u8)((RF) & 0xFF);
pr_info(" Data = %02x %02x %02x %02x %02x %02x\n",
pr_info("DDBridge: Data = %02x %02x %02x %02x %02x %02x\n",
Data[0], Data[1], Data[2], Data[3], Data[4], Data[5]);
mod_si598_writereg(dev, 7, Data[0]);
mod_si598_writereg(dev, 8, Data[1]);
@@ -866,11 +955,11 @@ static int mod_init_dac_input(struct ddb *dev)
}
if (Sample1 == 0xFF || Sample2 == 0xFF) {
pr_err(" No valid window found\n");
pr_err("DDBridge: No valid window found\n");
return -EINVAL;
}
pr_err(" Window = %d - %d\n", Sample1, Sample2);
pr_err("DDBridge: Window = %d - %d\n", Sample1, Sample2);
for (Sample = Sample1; Sample < Sample2; Sample += 1) {
if (SetTable[Sample] < HldTable[Sample]) {
@@ -881,15 +970,15 @@ static int mod_init_dac_input(struct ddb *dev)
}
}
pr_info("Select Sample %d\n", SelectSample);
pr_info("DDBridge: Select Sample %d\n", SelectSample);
if (SelectSample == 0xFF) {
pr_err("No valid sample found\n");
pr_err("DDBridge: No valid sample found\n");
return -EINVAL;
}
if (HldTable[SelectSample] + SetTable[SelectSample] < 8) {
pr_err("Too high jitter\n");
pr_err("DDBridge: Too high jitter\n");
return -EINVAL;
}
@@ -904,10 +993,10 @@ static int mod_init_dac_input(struct ddb *dev)
mod_read_dac_register(dev, 0x06, &ReadSeek);
Seek &= ReadSeek;
if ((Seek & 0x01) == 0) {
pr_err("Insufficient timing margin\n");
pr_err("DDBridge: Insufficient timing margin\n");
return -EINVAL;
}
pr_info("Done\n");
pr_info("DDBridge: Done\n");
return 0;
}
@@ -964,7 +1053,7 @@ static int mod_set_dac_clock(struct ddb *dev, u32 Frequency)
ddbwritel(dev, DAC_CONTROL_RESET, DAC_CONTROL);
msleep(20);
if (mod_set_si598(dev, Frequency)) {
pr_err("mod_set_si598 failed\n");
pr_err("DDBridge: mod_set_si598 failed\n");
return -1;
}
msleep(50);
@@ -979,7 +1068,7 @@ static int mod_set_dac_clock(struct ddb *dev, u32 Frequency)
break;
msleep(100);
}
pr_info("mod_set_dac_clock OK\n");
pr_info("DDBridge: mod_set_dac_clock OK\n");
return hr;
}
@@ -1063,17 +1152,6 @@ u32 eqtab[] = {
0x00001B23, 0x0000EEB7, 0x00006A28
};
static int mod_set_modulation(struct ddb *dev, int chan, enum fe_modulation mod)
{
if (mod > QAM_256 || mod < QAM_16)
return -EINVAL;
dev->mod[chan].modulation = mod;
dev->mod[chan].obitrate = 0x0061072787900000ULL * (mod + 3);
dev->mod[chan].ibitrate = dev->mod[chan].obitrate;
ddbwritel(dev, qamtab[mod], CHANNEL_SETTINGS(chan));
return 0;
}
static void mod_set_channelsumshift(struct ddb *dev, u32 shift)
{
ddbwritel(dev, (shift & 3) << 2, MODULATOR_CONTROL);
@@ -1096,18 +1174,18 @@ static int set_base_frequency(struct ddb *dev, u32 freq)
u32 UP2Frequency = 1896;
u32 down, freq10;
pr_info("set base to %u\n", freq);
pr_info("DDBridge: set base to %u\n", freq);
dev->mod_base.frequency = freq;
freq /= 1000000;
freq10 = dev->mod_base.flat_start + 4;
down = freq + 9 * 8 + freq10 + UP1Frequency + UP2Frequency;
if ((freq10 + 9 * 8) > (dev->mod_base.flat_end - 4)) {
pr_err("Frequency out of range %d\n", freq10);
pr_err("DDBridge: Frequency out of range %d\n", freq10);
return -EINVAL;
}
if (down % 8) {
pr_err(" Invalid Frequency %d\n", down);
pr_err("DDBridge: Invalid Frequency %d\n", down);
return -EINVAL;
}
return mod_set_down(dev, down, 8, Ext);
@@ -1136,12 +1214,12 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)
stat = -EINVAL;
goto fail;
}
pr_info("srate = %d\n", flash->DataSet[0].Symbolrate * 1000);
pr_info("DDBridge: srate = %d\n", flash->DataSet[0].Symbolrate * 1000);
mod_output_enable(dev, 0);
stat = mod_set_dac_clock(dev, flash->DataSet[0].DACFrequency * 1000);
if (stat < 0) {
pr_err("setting DAC clock failed\n");
pr_err("DDBridge: setting DAC clock failed\n");
goto fail;
}
mod_set_dac_current(dev, 512, 512);
@@ -1158,16 +1236,16 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)
FrequencyCH10 = flash->DataSet[0].FlatStart + 4;
DownFrequency = Frequency + 9 * 8 + FrequencyCH10 +
UP1Frequency + UP2Frequency;
pr_info("CH10 = %d, Down = %d\n", FrequencyCH10, DownFrequency);
pr_info("DDBridge: CH10 = %d, Down = %d\n", FrequencyCH10, DownFrequency);
if ((FrequencyCH10 + 9 * 8) > (flash->DataSet[0].FlatEnd - 4)) {
pr_err("Frequency out of range %d\n", FrequencyCH10);
pr_err("DDBridge: Frequency out of range %d\n", FrequencyCH10);
stat = -EINVAL;
goto fail;
}
if (DownFrequency % 8 != 0) {
pr_err(" Invalid Frequency %d\n", DownFrequency);
pr_err("DDBridge: Invalid Frequency %d\n", DownFrequency);
stat = -EINVAL;
goto fail;
}
@@ -1175,13 +1253,18 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)
mod_set_down(dev, DownFrequency, 8, Ext);
for (i = 0; i < 10; i++) {
struct ddb_mod *mod = &dev->mod[i];
mod->port = &dev->port[i];
ddbwritel(dev, 0, CHANNEL_CONTROL(i));
iqfreq = flash->DataSet[0].FrequencyFactor *
(FrequencyCH10 + (9 - i) * 8);
iqfreq += (dev->link[0].ids.hwid == 0x0203dd01) ? 22 : 0;
iqsteps = flash->DataSet[0].IQTableLength;
mod_set_iq(dev, iqsteps, i, iqfreq);
mod_set_modulation(dev, i, QAM_256);
mod_set_modulation(mod, QAM_256);
mod_set_symbolrate(mod, 6900000);
}
mod_bypass_equalizer(dev, 1);
@@ -1191,7 +1274,7 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)
flash->DataSet[0].PostScaleQ);
mod_pre_eq_gain(dev, flash->DataSet[0].PreScale);
/*mod_pre_eq_gain(dev, 0x0680);*/
pr_info("prescaler %04x\n", flash->DataSet[0].PreScale);
pr_info("DDBridge: prescaler %04x\n", flash->DataSet[0].PreScale);
mod_set_channelsumshift(dev, 2);
mod_output_enable(dev, 1);
@@ -1315,7 +1398,7 @@ void ddbridge_mod_rate_handler(unsigned long data)
case CM_ADJUST:
if (InPacketDiff < mod->MinInputPackets) {
pr_info("PCR Adjust reset IN: %u Min: %u\n",
pr_info("DDBridge: PCR Adjust reset IN: %u Min: %u\n",
InPacketDiff, mod->MinInputPackets);
mod->InPacketsSum = 0;
mod->OutPacketsSum = 0;
@@ -1356,7 +1439,7 @@ void ddbridge_mod_rate_handler(unsigned long data)
mod->PCRIncrement += PCRIncrementDiff;
pcr = ConvertPCR(mod->PCRIncrement);
pr_info("outl %016llx\n", pcr);
pr_info("DDBridge: outl %016llx\n", pcr);
ddbwritel(dev, pcr & 0xffffffff,
CHANNEL_PCR_ADJUST_OUTL(output->nr));
ddbwritel(dev, (pcr >> 32) & 0xffffffff,
@@ -1383,164 +1466,33 @@ void ddbridge_mod_rate_handler(unsigned long data)
spin_unlock(&dma->lock);
pr_info("chan %d out %016llx in %016llx indiff %08x\n",
pr_info("DDBridge: chan %d out %016llx in %016llx indiff %08x\n",
chan, OutPackets, InPackets, InPacketDiff);
pr_info("cnt %d pcra %016llx pcraext %08x pcraextfrac %08x pcrcorr %08x pcri %016llx\n",
pr_info("DDBridge: cnt %d pcra %016llx pcraext %08x pcraextfrac %08x pcrcorr %08x pcri %016llx\n",
mod->StateCounter, PCRAdjust, PCRAdjustExt,
PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement);
}
static int mod_ioctl_1(struct file *file, unsigned int cmd, void *parg)
static int mod_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
{
struct dvb_device *dvbdev = file->private_data;
struct ddb_output *output = dvbdev->priv;
struct ddb *dev = output->port->dev;
struct ddb *dev = mod->port->dev;
/* unsigned long arg = (unsigned long) parg; */
int ret = 0;
switch(tvp->cmd) {
case MODULATOR_SYMBOL_RATE:
return mod_set_symbolrate(mod, tvp->u.data);
switch (cmd) {
case DVB_MOD_SET:
{
struct dvb_mod_params *mp = parg;
case MODULATOR_MODULATION:
return mod_set_modulation(mod, tvp->u.data);
pr_info("set base freq\n");
if (mp->base_frequency != dev->mod_base.frequency)
if (set_base_frequency(dev, mp->base_frequency))
return -EINVAL;
pr_info("set attenuator\n");
mod_set_attenuator(dev, mp->attenuator);
break;
case MODULATOR_FREQUENCY:
return mod_set_frequency(mod, tvp->u.data);
case MODULATOR_ATTENUATOR:
return mod_set_attenuator(mod->port->dev, tvp->u.data);
case MODULATOR_INPUT_BITRATE:
return mod_set_ibitrate(mod, tvp->u.data);
}
case DVB_MOD_CHANNEL_SET:
{
struct dvb_mod_channel_params *cp = parg;
int res;
u32 ri;
pr_info("set modulation\n");
res = mod_set_modulation(dev, output->nr, cp->modulation);
if (res)
return res;
if (cp->input_bitrate > dev->mod[output->nr].obitrate)
return -EINVAL;
dev->mod[output->nr].ibitrate = cp->input_bitrate;
dev->mod[output->nr].pcr_correction = cp->pcr_correction;
pr_info("ibitrate %llu\n", dev->mod[output->nr].ibitrate);
pr_info("obitrate %llu\n", dev->mod[output->nr].obitrate);
if (cp->input_bitrate != 0) {
u64 d = dev->mod[output->nr].obitrate -
dev->mod[output->nr].ibitrate;
d = div64_u64(d, dev->mod[output->nr].obitrate >> 24);
if (d > 0xfffffe)
ri = 0xfffffe;
else
ri = d;
} else
ri = 0;
dev->mod[output->nr].rate_inc = ri;
pr_info("ibr=%llu, obr=%llu, ri=0x%06x\n",
dev->mod[output->nr].ibitrate >> 32,
dev->mod[output->nr].obitrate >> 32,
ri);
break;
}
default:
ret = -EINVAL;
break;
}
return ret;
}
/****************************************************************************/
/****************************************************************************/
/****************************************************************************/
static int mod_ioctl_2(struct file *file, unsigned int cmd, void *parg)
{
struct dvb_device *dvbdev = file->private_data;
struct ddb_output *output = dvbdev->priv;
struct ddb *dev = output->port->dev;
/* unsigned long arg = (unsigned long) parg; */
int ret = 0;
switch (cmd) {
case DVB_MOD_SET:
{
struct dvb_mod_params *mp = parg;
pr_info("set base freq\n");
dev->mod_base.frequency = mp->base_frequency;
pr_info("set attenuator\n");
mod_set_attenuator(dev, mp->attenuator);
break;
}
case DVB_MOD_CHANNEL_SET:
{
struct dvb_mod_channel_params *cp = parg;
int res;
u32 ri;
pr_info("set modulation\n");
res = mod_set_modulation(dev, output->nr, cp->modulation);
if (res)
return res;
if (cp->input_bitrate > dev->mod[output->nr].obitrate)
return -EINVAL;
dev->mod[output->nr].ibitrate = cp->input_bitrate;
dev->mod[output->nr].pcr_correction = cp->pcr_correction;
pr_info("ibitrate %llu\n", dev->mod[output->nr].ibitrate);
pr_info("obitrate %llu\n", dev->mod[output->nr].obitrate);
if (cp->input_bitrate != 0) {
u64 d = dev->mod[output->nr].obitrate -
dev->mod[output->nr].ibitrate;
d = div64_u64(d, dev->mod[output->nr].obitrate >> 24);
if (d > 0xfffffe)
ri = 0xfffffe;
else
ri = d;
} else
ri = 0;
dev->mod[output->nr].rate_inc = ri;
pr_info("ibr=%llu, obr=%llu, ri=0x%06x\n",
dev->mod[output->nr].ibitrate >> 32,
dev->mod[output->nr].obitrate >> 32,
ri);
break;
}
default:
ret = -EINVAL;
break;
}
return ret;
}
static int mod_init_2(struct ddb *dev, u32 Frequency)
{
int status;
int streams = dev->link[0].info->port_num;
dev->mod_base.frequency = Frequency;
mod_TemperatureMonitorInit(dev, 1);
status = mod_fsm_setup(dev, 0, 0);
if (streams <= 8)
mod_set_vga(dev, RF_VGA_GAIN_N8);
else if (streams <= 16)
mod_set_vga(dev, RF_VGA_GAIN_N16);
else
mod_set_vga(dev, RF_VGA_GAIN_N24);
mod_set_attenuator(dev, 0);
return 0;
}
@@ -1549,17 +1501,114 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
struct dvb_device *dvbdev = file->private_data;
struct ddb_output *output = dvbdev->priv;
struct ddb *dev = output->port->dev;
struct ddb_mod *mod = &dev->mod[output->nr];
int ret = 0;
switch (cmd) {
case FE_SET_PROPERTY:
{
struct dtv_properties *tvps = (struct dtv_properties __user *) parg;
struct dtv_property *tvp = NULL;
int i;
if ((tvps->num == 0) || (tvps->num > DTV_IOCTL_MAX_MSGS))
return -EINVAL;
tvp = kmalloc(tvps->num * sizeof(struct dtv_property), GFP_KERNEL);
if (!tvp) {
ret = -ENOMEM;
goto out;
}
if (copy_from_user(tvp, tvps->props, tvps->num *
sizeof(struct dtv_property))) {
ret = -EFAULT;
goto out;
}
for (i = 0; i < tvps->num; i++) {
if ((ret = mod_prop_proc(mod, tvp + i)) < 0)
goto out;
(tvp + i)->result = ret;
}
out:
kfree(tvp);
return ret;
}
case DVB_MOD_SET:
{
struct dvb_mod_params *mp = parg;
if (dev->link[0].info->version < 2) {
if (mp->base_frequency != dev->mod_base.frequency)
if (set_base_frequency(dev, mp->base_frequency))
return -EINVAL;
} else {
int i, streams = dev->link[0].info->port_num;
dev->mod_base.frequency = mp->base_frequency;
for (i = 0; i < streams; i++) {
struct ddb_mod *mod = &dev->mod[i];
mod->port = &dev->port[i];
mod_set_modulation(mod, QAM_256);
mod_set_symbolrate(mod, 6900000);
mod_set_frequency(mod, dev->mod_base.frequency +
i * 8000000);
}
}
mod_set_attenuator(dev, mp->attenuator);
break;
}
case DVB_MOD_CHANNEL_SET:
{
struct dvb_mod_channel_params *cp = parg;
struct ddb_mod *mod = &dev->mod[output->nr];
int res;
res = mod_set_modulation(mod, cp->modulation);
if (res)
return res;
res = mod_set_ibitrate(mod, cp->input_bitrate);
if (res)
return res;
mod->pcr_correction = cp->pcr_correction;
break;
}
default:
ret = -EINVAL;
break;
}
return ret;
}
static int mod_init_2(struct ddb *dev, u32 Frequency)
{
int status, i;
int streams = dev->link[0].info->port_num;
dev->mod_base.frequency = Frequency;
status = mod_fsm_setup(dev, 0, 0);
for (i = 0; i < streams; i++) {
struct ddb_mod *mod = &dev->mod[i];
mod->port = &dev->port[i];
mod_set_modulation(mod, QAM_256);
mod_set_symbolrate(mod, 6900000);
mod_set_frequency(mod, 114000000 + i * 8000000);
}
if (streams <= 8)
mod_set_vga(dev, RF_VGA_GAIN_N8);
else if (streams <= 16)
mod_set_vga(dev, RF_VGA_GAIN_N16);
else
mod_set_vga(dev, RF_VGA_GAIN_N24);
if (dev->link[0].info->version <= 0)
return mod_ioctl_1(file, cmd, parg);
if (dev->link[0].info->version == 2)
return mod_ioctl_2(file, cmd, parg);
return -1;
mod_set_attenuator(dev, 0);
return 0;
}
int ddbridge_mod_init(struct ddb *dev)
{
spin_lock_init(&dev->mod_base.temp_lock);
if (dev->link[0].info->version <= 1)
return mod_init_1(dev, 722000000);
if (dev->link[0].info->version == 2)

4
ddbridge/ddbridge-ns.c
View File

@@ -87,7 +87,7 @@ static int ns_alloc(struct dvbnss *nss)
dev->ns[i].fe = input;
nss->priv = &dev->ns[i];
ret = 0;
/*pr_info("%s i=%d fe=%d\n", __func__, i, input->nr); */
/*pr_info("DDBridge: %s i=%d fe=%d\n", __func__, i, input->nr); */
break;
}
ddbwritel(dev, 0x03, RTP_MASTER_CONTROL);
@@ -198,7 +198,7 @@ static int ns_set_ci(struct dvbnss *nss, u8 ci)
if (ciport < 0)
return -EINVAL;
pr_info("input %d.%d to ci %d at port %d\n",
pr_info("DDBridge: input %d.%d to ci %d at port %d\n",
input->port->lnr, input->nr, ci, ciport);
ddbwritel(dev, (input->port->lnr << 21) | (input->nr << 16) | 0x1c,
TS_CONTROL(dev->port[ciport].output));

2
ddbridge/ddbridge-regs.h
View File

@@ -147,7 +147,7 @@
#define DAC_CONTROL_RESET (0x200)
/* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */
#define TEMPMON_BASE (0xA0)
#define TEMPMON_BASE (0x1c0)
#define TEMPMON_CONTROL (TEMPMON_BASE + 0x00)
#define TEMPMON_CONTROL_SCAN (0x00000001)

46
ddbridge/ddbridge.c
View File

@@ -147,7 +147,7 @@ static int __devinit ddb_irq_init2(struct ddb *dev)
int stat;
int irq_flag = IRQF_SHARED;
pr_info("init type 2 IRQ hardware block\n");
pr_info("DDBridge: init type 2 IRQ hardware block\n");
ddbwritel(dev, 0x00000000, INTERRUPT_V2_CONTROL);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_1);
@@ -268,7 +268,7 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
dev->link[0].dev = dev;
dev->link[0].info = (struct ddb_info *) id->driver_data;
pr_info("DDBridge driver detected: %s\n", dev->link[0].info->name);
pr_info("DDBridge: device name: %s\n", dev->link[0].info->name);
dev->regs_len = pci_resource_len(dev->pdev, 0);
dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
@@ -313,11 +313,11 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
ddb_irq_disable(dev);
fail0:
pr_err("fail0\n");
pr_err("DDBridge: fail0\n");
if (dev->msi)
pci_disable_msi(dev->pdev);
fail:
pr_err("fail\n");
pr_err("DDBridge: fail\n");
ddb_unmap(dev);
pci_set_drvdata(pdev, NULL);
@@ -395,6 +395,17 @@ static struct ddb_info ddb_v6_5 = {
.i2c_mask = 0x0f,
};
static struct ddb_info ddb_v7a = {
.type = DDB_OCTOPUS,
.name = "Digital Devices Cine S2 V7 Advanced DVB adapter",
.regmap = &octopus_map,
.port_num = 4,
.i2c_mask = 0x0f,
.board_control = 2,
.board_control_2 = 4,
.ts_quirks = TS_QUIRK_REVERSED,
};
static struct ddb_info ddb_v7 = {
.type = DDB_OCTOPUS,
.name = "Digital Devices Cine S2 V7 DVB adapter",
@@ -450,6 +461,16 @@ static struct ddb_info ddb_ci_s2_pro = {
.board_control_2 = 4,
};
static struct ddb_info ddb_ci_s2_pro_a = {
.type = DDB_OCTOPUS_CI,
.name = "Digital Devices Octopus CI S2 Pro Advanced",
.regmap = &octopus_map,
.port_num = 4,
.i2c_mask = 0x01,
.board_control = 2,
.board_control_2 = 4,
};
static struct ddb_info ddb_dvbct = {
.type = DDB_OCTOPUS,
.name = "Digital Devices DVBCT V6.1 DVB adapter",
@@ -475,6 +496,7 @@ static struct ddb_info ddb_mod_fsm_24 = {
.regmap = &octopus_mod_2_map,
.port_num = 24,
.temp_num = 1,
.tempmon_irq = 8,
};
static struct ddb_info ddb_mod_fsm_16 = {
@@ -484,6 +506,7 @@ static struct ddb_info ddb_mod_fsm_16 = {
.regmap = &octopus_mod_2_map,
.port_num = 16,
.temp_num = 1,
.tempmon_irq = 8,
};
static struct ddb_info ddb_mod_fsm_8 = {
@@ -493,6 +516,7 @@ static struct ddb_info ddb_mod_fsm_8 = {
.regmap = &octopus_mod_2_map,
.port_num = 8,
.temp_num = 1,
.tempmon_irq = 8,
};
static struct ddb_info ddb_octopro_hdin = {
@@ -535,21 +559,27 @@ static const struct pci_device_id ddb_id_tbl[] __devinitconst = {
DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6),
DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5),
DDB_ID(DDVID, 0x0006, DDVID, 0x0022, ddb_v7),
DDB_ID(DDVID, 0x0006, DDVID, 0x0024, ddb_v7a),
DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct),
DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3),
DDB_ID(DDVID, 0x0006, DDVID, 0x0031, ddb_ctv7),
DDB_ID(DDVID, 0x0006, DDVID, 0x0032, ddb_ctv7),
DDB_ID(DDVID, 0x0006, DDVID, 0x0033, ddb_ctv7),
DDB_ID(DDVID, 0x0007, DDVID, 0x0023, ddb_s2_48),
DDB_ID(DDVID, 0x0008, DDVID, 0x0034, ddb_ct_8),
DDB_ID(DDVID, 0x0008, DDVID, 0x0035, ddb_ct_8),
DDB_ID(DDVID, 0x0008, DDVID, 0x0036, ddb_ct_8),
DDB_ID(DDVID, 0x0008, DDVID, 0x0034, ddb_ct2_8),
DDB_ID(DDVID, 0x0008, DDVID, 0x0035, ddb_c2t2_8),
DDB_ID(DDVID, 0x0008, DDVID, 0x0036, ddb_isdbt_8),
DDB_ID(DDVID, 0x0008, DDVID, 0x0037, ddb_c2t2i_v0_8),
DDB_ID(DDVID, 0x0008, DDVID, 0x0038, ddb_c2t2i_8),
DDB_ID(DDVID, 0x0006, DDVID, 0x0039, ddb_ctv7),
DDB_ID(DDVID, 0x0011, DDVID, 0x0040, ddb_ci),
DDB_ID(DDVID, 0x0011, DDVID, 0x0041, ddb_cis),
DDB_ID(DDVID, 0x0012, DDVID, 0x0042, ddb_ci),
DDB_ID(DDVID, 0x0013, DDVID, 0x0043, ddb_ci_s2_pro),
DDB_ID(DDVID, 0x0013, DDVID, 0x0044, ddb_ci_s2_pro_a),
DDB_ID(DDVID, 0x0201, DDVID, 0x0001, ddb_mod),
DDB_ID(DDVID, 0x0201, DDVID, 0x0002, ddb_mod),
DDB_ID(DDVID, 0x0203, DDVID, 0x0001, ddb_mod),
DDB_ID(DDVID, 0x0210, DDVID, 0x0001, ddb_mod_fsm_24),
DDB_ID(DDVID, 0x0210, DDVID, 0x0002, ddb_mod_fsm_16),
DDB_ID(DDVID, 0x0210, DDVID, 0x0003, ddb_mod_fsm_8),
@@ -585,7 +615,7 @@ static __init int module_init_ddbridge(void)
{
int stat = -1;
pr_info("Digital Devices PCIE bridge driver "
pr_info("DDBridge: Digital Devices PCIE bridge driver "
DDBRIDGE_VERSION
", Copyright (C) 2010-16 Digital Devices GmbH\n");
if (ddb_class_create() < 0)

27
ddbridge/ddbridge.h
View File

@@ -113,7 +113,7 @@ struct ddb_regmap {
u32 irq_base_odma;
u32 irq_base_gtl;
u32 irq_base_rate;
struct ddb_regset *i2c;
struct ddb_regset *i2c_buf;
struct ddb_regset *idma;
@@ -172,6 +172,8 @@ struct ddb_info {
#define TS_QUIRK_SERIAL 1
#define TS_QUIRK_REVERSED 2
#define TS_QUIRK_NO_OUTPUT 4
#define TS_QUIRK_ALT_OSC 8
u32 tempmon_irq;
struct ddb_regmap *regmap;
};
@@ -182,11 +184,11 @@ struct ddb_info {
#ifdef SMALL_DMA_BUFS
#define INPUT_DMA_BUFS 32
#define INPUT_DMA_SIZE (32*47*21)
#define INPUT_DMA_SIZE (128*47*5)
#define INPUT_DMA_IRQ_DIV 1
#define OUTPUT_DMA_BUFS 32
#define OUTPUT_DMA_SIZE (32*47*21)
#define OUTPUT_DMA_SIZE (128*47*5)
#define OUTPUT_DMA_IRQ_DIV 1
#else
#define INPUT_DMA_BUFS 8
@@ -316,6 +318,7 @@ struct ddb_port {
#define DDB_CI_EXTERNAL_XO2 12
#define DDB_CI_EXTERNAL_XO2_B 13
#define DDB_TUNER_DVBS_STV0910_PR 14
#define DDB_TUNER_DVBC2T2I_SONY_P 15
#define DDB_TUNER_XO2 32
#define DDB_TUNER_DVBS_STV0910 (DDB_TUNER_XO2 + 0)
@@ -323,7 +326,7 @@ struct ddb_port {
#define DDB_TUNER_ISDBT_SONY (DDB_TUNER_XO2 + 2)
#define DDB_TUNER_DVBC2T2_SONY (DDB_TUNER_XO2 + 3)
#define DDB_TUNER_ATSC_ST (DDB_TUNER_XO2 + 4)
#define DDB_TUNER_DVBC2T2_ST (DDB_TUNER_XO2 + 5)
#define DDB_TUNER_DVBC2T2I_SONY (DDB_TUNER_XO2 + 5)
struct ddb_input *input[2];
struct ddb_output *output;
@@ -338,10 +341,6 @@ struct mod_base {
u32 frequency;
u32 flat_start;
u32 flat_end;
spinlock_t temp_lock;
int OverTemperatureError;
u8 temp_tab[11];
};
struct ddb_mod {
@@ -424,6 +423,10 @@ struct ddb_link {
struct ddb_lnb lnb;
struct tasklet_struct tasklet;
struct ddb_ids ids;
spinlock_t temp_lock;
int OverTemperatureError;
u8 temp_tab[11];
};
struct ddb {
@@ -471,6 +474,7 @@ struct ddb {
struct mod_base mod_base;
struct ddb_mod mod[24];
};
static inline void ddbwriteb(struct ddb *dev, u32 val, u32 adr)
@@ -520,7 +524,7 @@ static inline void gtlw(struct ddb_link *link)
}
#endif
#if 0
static u32 ddblreadl(struct ddb_link *link, u32 adr)
{
if (unlikely(link->nr)) {
@@ -554,7 +558,6 @@ static void ddblwritel(struct ddb_link *link, u32 val, u32 adr)
}
writel(val, (char *) (link->dev->regs + (adr)));
}
#endif
static u32 ddbreadl(struct ddb *dev, u32 adr)
{
@@ -744,12 +747,12 @@ struct DDMOD_FLASH {
int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg);
int ddbridge_mod_init(struct ddb *dev);
void ddbridge_mod_output_stop(struct ddb_output *output);
void ddbridge_mod_output_start(struct ddb_output *output);
int ddbridge_mod_output_start(struct ddb_output *output);
void ddbridge_mod_rate_handler(unsigned long data);
int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len);
#define DDBRIDGE_VERSION "0.9.24"
#define DDBRIDGE_VERSION "0.9.28"
#endif

6
ddbridge/octonet.c
View File

@@ -177,9 +177,9 @@ static int __init octonet_probe(struct platform_device *pdev)
else
dev->link[0].info = &ddb_octonet_tbd;
pr_info("HW %08x REGMAP %08x\n",
pr_info("DDBridge: HW %08x REGMAP %08x\n",
dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
pr_info("MAC %08x DEVID %08x\n",
pr_info("DDBridge: MAC %08x DEVID %08x\n",
dev->link[0].ids.mac, dev->link[0].ids.devid);
ddbwritel(dev, 0, ETHER_CONTROL);
@@ -233,7 +233,7 @@ static __init int init_octonet(void)
{
int res;
pr_info("Digital Devices OctopusNet driver " DDBRIDGE_VERSION
pr_info("DDBridge: Digital Devices OctopusNet driver " DDBRIDGE_VERSION
", Copyright (C) 2010-16 Digital Devices GmbH\n");
res = ddb_class_create();
if (res)

625
frontends/cxd2843.c
View File

File diff suppressed because it is too large Load Diff

1
frontends/cxd2843.h
View File

@@ -8,6 +8,7 @@ struct cxd2843_cfg {
u8 adr;
u32 ts_clock;
u8 parallel;
u32 osc;
};
#if defined(CONFIG_DVB_CXD2843) || \

6
frontends/mxl5xx.c
View File

@@ -698,6 +698,10 @@ static int read_signal_strength(struct dvb_frontend *fe, u16 *strength)
int stat;
u32 regData = 0;
#if 0
if (!firmware_is_alive(state))
pr_info("FW dead!\n");
#endif
mutex_lock(&state->base->status_lock);
HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR +
@@ -1639,7 +1643,7 @@ static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg)
static int validate_sku(struct mxl *state)
{
u32 padMuxBond, prcmChipId, prcmSoCId;
u32 padMuxBond = 0, prcmChipId = 0, prcmSoCId = 0;
int status;
u32 type = state->base->type;

63
frontends/stv090x.c
View File

@@ -5144,69 +5144,6 @@ static int stv090x_get_frontend(struct dvb_frontend *fe)
return 0;
}
static int get_frontend(struct dvb_frontend *fe)
{
struct stv090x_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
u8 tmp;
u32 reg = 0;
if (state->rec_mode == 2) {
u32 mc;
enum fe_modulation modcod2mod[0x20] = {
QPSK, QPSK, QPSK, QPSK,
QPSK, QPSK, QPSK, QPSK,
QPSK, QPSK, QPSK, QPSK,
PSK_8, PSK_8, PSK_8, PSK_8,
PSK_8, PSK_8, APSK_16, APSK_16,
APSK_16, APSK_16, APSK_16, APSK_16,
APSK_32, APSK_32, APSK_32, APSK_32,
APSK_32,
};
enum fe_code_rate modcod2fec[0x20] = {
FEC_NONE, FEC_1_4, FEC_1_3, FEC_2_5,
FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
FEC_9_10
};
mc = state->modcod;
p->pilot = (state->pilots & 0x01) ? PILOT_ON : PILOT_OFF;
p->modulation = modcod2mod[mc];
p->fec_inner = modcod2fec[mc];
} else if (state->rec_mode == 1) {
reg = STV090x_READ_DEMOD(state, VITCURPUN);
switch( reg & 0x1F ) {
case 0x0d:
p->fec_inner = FEC_1_2;
break;
case 0x12:
p->fec_inner = FEC_2_3;
break;
case 0x15:
p->fec_inner = FEC_3_4;
break;
case 0x18:
p->fec_inner = FEC_5_6;
break;
case 0x1a:
p->fec_inner = FEC_7_8;
break;
default:
p->fec_inner = FEC_NONE;
break;
}
p->rolloff = ROLLOFF_35;
} else {
}
return 0;
}
static struct dvb_frontend_ops stv090x_ops = {
#ifndef USE_API3
.delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },

16
frontends/stv0910.c
View File

@@ -105,6 +105,7 @@ struct stv {
u8 tscfgh;
u8 tsgeneral;
u8 tsspeed;
u8 single;
unsigned long tune_time;
s32 SearchRange;
@@ -1137,7 +1138,13 @@ static int probe(struct stv *state)
write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */
write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */
write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
if (state->single)
write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
else
write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
@@ -1251,7 +1258,7 @@ static int get_frequency_offset(struct stv *state, s32 *off)
derot = ((u32) cfr2 << 16) | ((u32)cfr1 << 8) | cfr0;
if (derot & (1<<23))
derot |= 0xFF000000;
*off = - (s32) (((s64) derot * (s64) state->base->mclk) >> 24);
*off = (s32) (((s64) derot * (s64) state->base->mclk) >> 24);
//pr_info("foff = %d\n", *off);
return 0;
}
@@ -1359,6 +1366,7 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status)
u32 ber;
s32 foff;
*status = 0;
get_frequency_offset(state, &foff);
read_signal_strength(fe, &val);
@@ -1378,7 +1386,6 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status)
if (CurReceiveMode == Mode_None) {
set_vth(state);
//if( Time >= m_DemodTimeout ) *pLockStatus = NEVER_LOCK;
*status = 0;
return 0;
}
*status |= 0x0f;
@@ -1827,7 +1834,8 @@ struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
state->DEMOD = 0x10; /* Inversion : Auto with reset to 0 */
state->ReceiveMode = Mode_None;
state->CurScramblingCode = NO_SCRAMBLING_CODE;
state->single = cfg->single ? 1 : 0;
base = match_base(i2c, cfg->adr);
if (base) {
base->count++;

1
frontends/stv0910.h
View File

@@ -9,6 +9,7 @@ struct stv0910_cfg {
u8 adr;
u8 parallel;
u8 rptlvl;
u8 single;
};
#if defined(CONFIG_DVB_STV0910) || \

11
include/linux/dvb/mod.h
View File

@@ -19,4 +19,15 @@ struct dvb_mod_channel_params {
#define DVB_MOD_SET _IOW('o', 208, struct dvb_mod_params)
#define DVB_MOD_CHANNEL_SET _IOW('o', 209, struct dvb_mod_channel_params)
#define MODULATOR_UNDEFINED 0
#define MODULATOR_START 1
#define MODULATOR_STOP 2
#define MODULATOR_FREQUENCY 3
#define MODULATOR_MODULATION 4
#define MODULATOR_SYMBOL_RATE 5 /* Hz */
#define MODULATOR_ATTENUATOR 32
#define MODULATOR_INPUT_BITRATE 33 /* Hz */
#define MODULATOR_PCR_MODE 34 /* 1=pcr correction enabled */
#endif /*_UAPI_DVBMOD_H_*/